Closed
Milestone
started on Nov 16, 2020
layout v1.0
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
54
- L4 (X:192mm Y:54mm) P3V3 plane unnecessairly cuts into PPERIPH plane and therefore cuts plane below L3 signals
- 12V from the backplane connector could use more copper
- No stock for some components, can we replace them?
- IC6: missing input voltage
- JTAG pull-ups and pull-downs
- Wrong pull ups at voltage translators (IC7)
- Capacitor V-Ratings
- LC filter layout can be improved
- P2V5_A rail is unused, it has to be removed
- IC6: TPS7A4533 Does not have enough copper at Pad 6 for heat dissipation.
- P_PRES[0,1] missing pull-ups
- PWR_FAIL_N missing pull-up
- Different packages used for IC4 and IC5 (both TPS7A4901)
- Different kind of Vias...
- Stack Up Layer Legend does not match the stack up
- Board guide
- C102 not directly connected to IC22
- C180 is placed Under FPGA and not IC32
- IC27 : Decoupling capacitor placed on wrong pin
- MONIMOD I2C lines close to monitoring signals
- Stray Lines and Via on FMC-JTAG.TMS line
- DC blocking caps routing
- Missing return vias (GND Vias) on serdes signals
- Placement of SERDES resistor and decoupling cap.
- Skew compensation
- Vias sharing and decoupling caps net width
- Stray line on SD_PLL_VSSA
- Routing of VDDPLL and PLLVSSA should be done with Planes not traces
- Decoupling Caps for FPGA are using Vias on Pads that are not Capped and Filled.
- Stray track on PPERIPH net and Keep out region
- Acid Traps
- PGOOD.P3V3 Splits polygon
- Analog power filtering area
- IC20 and IC34 : TPS7A4901 Layout guidelines are not respected
- L1 Common mode choke connection is not ok
- Power dissipation of LT3083 for 2.5V
- P2V5 supply not well connected
- P12V_CPCIS net needs a plane or more copper.
- L1: missing exposed GND plane between backplane P3 and P4 connectors
- L6 X: 197mm Y: 83.5mm track not properly connected to via
- L1 (X: 114mm Y: 87mm) Poorly attached part of a polygon
- some FMC GND pads could connect to their own vias (already placed) instead of sharing with another FMC GND pad
- Remove leftovers from previous routing + cleanup some traces at vias
- Silkscreen licensing, EDA number and logo
- oscillator decoupling capacitors
- 2.5V power plane
- vias on smd pads
- bottom ground plane
- reduce track length on decoupling capacitors
- improve layout for some pairs
- check length matching on diff pairs
- right angles on diff pair accordions
- relief connect on power smd components
- relief connect on press-fit connectors