This modification has to be double-checked as:
1. it's not certain that we will reach the front panel, anyway, and
2. there are holes at the board's edge, to be checked if that's
allowed in our case.

Also, improve FPGA decoupling (fit more caps near the pins, reposition
others to minimize via sharing, etc)

Also move some capacitors to the front side.

Also reduce GND via sharing and generally improve somewhat the FPGA
decoupling capacitor placement.

Also improved routing for dual-purpose FMC JTAG stubs (see #81).

The rule about small holes (<0.5mm) mistakenly covered all SMD pads,
leading to very thin copper connections in thermal reliefs.