Commit f3f5d642 authored by Christos Gentsos's avatar Christos Gentsos

Configure FPGA pin- and pair-swapping groups

parent d8f60bd6
...@@ -49,9 +49,9 @@ Configuration1_Name1=OutputConfigurationParameter1 ...@@ -49,9 +49,9 @@ Configuration1_Name1=OutputConfigurationParameter1
Configuration1_Item1=Record=SchPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle|ShowNote=True|ShowNoteCollapsed=True|ShowOpenEnds=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False|PrintArea=0|PrintAreaRect.X1=0|PrintAreaRect.Y1=0|PrintAreaRect.X2=0|PrintAreaRect.Y2=0 Configuration1_Item1=Record=SchPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle|ShowNote=True|ShowNoteCollapsed=True|ShowOpenEnds=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False|PrintArea=0|PrintAreaRect.X1=0|PrintAreaRect.Y1=0|PrintAreaRect.X2=0|PrintAreaRect.Y2=0
[PublishSettings] [PublishSettings]
OutputFilePath2=\\cern.ch\dfs\Users\c\cgentsos\Documents\Altium projects\DIOT-sb-igl\hw\.PDF OutputFilePath2=D:\Altium projects\DIOT-sb-igl\hw\.\DIOT-sb-igl.pdf
ReleaseManaged2=0 ReleaseManaged2=0
OutputBasePath2=\\cern.ch\dfs\Users\c\cgentsos\Documents\Altium projects\DIOT-sb-igl\hw\ OutputBasePath2=.\
OutputPathMedia2= OutputPathMedia2=
OutputPathMediaValue2= OutputPathMediaValue2=
OutputPathOutputer2=[Output Type] OutputPathOutputer2=[Output Type]
...@@ -128,7 +128,7 @@ WmvVideoCodecName4=Windows Media Video V7 ...@@ -128,7 +128,7 @@ WmvVideoCodecName4=Windows Media Video V7
WmvQuality4=80 WmvQuality4=80
[GeneratedFilesSettings] [GeneratedFilesSettings]
RelativeOutputPath2=\\cern.ch\dfs\Users\c\cgentsos\Documents\Altium projects\DIOT-sb-igl\hw\.PDF RelativeOutputPath2=D:\Altium projects\DIOT-sb-igl\hw\.\DIOT-sb-igl.pdf
OpenOutputs2=0 OpenOutputs2=0
RelativeOutputPath3= RelativeOutputPath3=
OpenOutputs3=0 OpenOutputs3=0
......
...@@ -11,7 +11,7 @@ TimestampOutput=0 ...@@ -11,7 +11,7 @@ TimestampOutput=0
SeparateFolders=1 SeparateFolders=1
TemplateLocationPath= TemplateLocationPath=
PinSwapBy_Netlabel=1 PinSwapBy_Netlabel=1
PinSwapBy_Pin=1 PinSwapBy_Pin=0
AllowPortNetNames=0 AllowPortNetNames=0
AllowSheetEntryNetNames=0 AllowSheetEntryNetNames=0
AppendSheetNumberToLocalNets=0 AppendSheetNumberToLocalNets=0
...@@ -569,16 +569,16 @@ Path=G:\Applications\Altium\CernLib\*.* ...@@ -569,16 +569,16 @@ Path=G:\Applications\Altium\CernLib\*.*
IncludeSubFolders=0 IncludeSubFolders=0
[Parameter1] [Parameter1]
Name=Department Name=ProjectName
Value=BE/CO Value=DI/OT Rad-tol System Board
[Parameter2] [Parameter2]
Name=DrawnBy Name=DrawnBy
Value=C. Gentsos Value=C. Gentsos
[Parameter3] [Parameter3]
Name=ProjectName Name=Department
Value=DI/OT Rad-tol System Board Value=BE/CO
[Configuration1] [Configuration1]
Name=Sources Name=Sources
......
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