Configure FPGA pin- and pair-swapping groups

f3f5d642 · Christos Gentsos · d8f60bd6 · f3f5d642 · f3f5d642 · f3f5d642
Commit f3f5d642 authored Nov 16, 2020 by Christos Gentsos
8 changed files
--- a/hw/DIOT-sb-igl.OutJob
+++ b/hw/DIOT-sb-igl.OutJob
@@ -49,9 +49,9 @@ Configuration1_Name1=OutputConfigurationParameter1
 Configuration1_Item1=Record=SchPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle|ShowNote=True|ShowNoteCollapsed=True|ShowOpenEnds=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False|PrintArea=0|PrintAreaRect.X1=0|PrintAreaRect.Y1=0|PrintAreaRect.X2=0|PrintAreaRect.Y2=0

 [PublishSettings]
-OutputFilePath2=\\cern.ch\dfs\Users\c\cgentsos\Documents\Altium projects\DIOT-sb-igl\hw\.PDF
+OutputFilePath2=D:\Altium projects\DIOT-sb-igl\hw\.\DIOT-sb-igl.pdf
 ReleaseManaged2=0
-OutputBasePath2=\\cern.ch\dfs\Users\c\cgentsos\Documents\Altium projects\DIOT-sb-igl\hw\
+OutputBasePath2=.\
 OutputPathMedia2=
 OutputPathMediaValue2=
 OutputPathOutputer2=[Output Type]
@@ -128,7 +128,7 @@ WmvVideoCodecName4=Windows Media Video V7
 WmvQuality4=80

 [GeneratedFilesSettings]
-RelativeOutputPath2=\\cern.ch\dfs\Users\c\cgentsos\Documents\Altium projects\DIOT-sb-igl\hw\.PDF
+RelativeOutputPath2=D:\Altium projects\DIOT-sb-igl\hw\.\DIOT-sb-igl.pdf
 OpenOutputs2=0
 RelativeOutputPath3=
 OpenOutputs3=0

--- a/hw/DIOT-sb-igl.PrjPcb
+++ b/hw/DIOT-sb-igl.PrjPcb
@@ -11,7 +11,7 @@ TimestampOutput=0
 SeparateFolders=1
 TemplateLocationPath=
 PinSwapBy_Netlabel=1
-PinSwapBy_Pin=1
+PinSwapBy_Pin=0
 AllowPortNetNames=0
 AllowSheetEntryNetNames=0
 AppendSheetNumberToLocalNets=0
@@ -569,16 +569,16 @@ Path=G:\Applications\Altium\CernLib\*.*
 IncludeSubFolders=0

 [Parameter1]
-Name=Department
-Value=BE/CO
+Name=ProjectName
+Value=DI/OT Rad-tol System Board

 [Parameter2]
 Name=DrawnBy
 Value=C. Gentsos

 [Parameter3]
-Name=ProjectName
-Value=DI/OT Rad-tol System Board
+Name=Department
+Value=BE/CO

 [Configuration1]
 Name=Sources

--- a/hw/PCB-Layout/DIOT-sb-igl_pcb.PcbDoc
+++ b/hw/PCB-Layout/DIOT-sb-igl_pcb.PcbDoc
--- a/hw/Schematics/FPGA_Banks_0_3_5_8.SchDoc
+++ b/hw/Schematics/FPGA_Banks_0_3_5_8.SchDoc
--- a/hw/Schematics/FPGA_Banks_1_2.SchDoc
+++ b/hw/Schematics/FPGA_Banks_1_2.SchDoc
--- a/hw/Schematics/FPGA_Banks_6_7.SchDoc
+++ b/hw/Schematics/FPGA_Banks_6_7.SchDoc
--- a/hw/Schematics/FPGA_Config.SchDoc
+++ b/hw/Schematics/FPGA_Config.SchDoc
--- a/hw/Schematics/FPGA_Power.SchDoc
+++ b/hw/Schematics/FPGA_Power.SchDoc