- 21 Jul, 2017 6 commits
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Lucas Russo authored
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Lucas Russo authored
In this way, we can reset MMCM by software
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Lucas Russo authored
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Lucas Russo authored
This will be used manually reset the ADC MMCM by software, every time a clock change happens.
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Lucas Russo authored
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Lucas Russo authored
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- 20 Jul, 2017 1 commit
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Lucas Russo authored
Now, on asserting LOCKED by MMCM, we synchronize it to the destination clock domain and waits until the LOCK signal has stabilized for a few clock cycles. In this way we can safely use the mmcm_adc_locked signal as a reset to downstream logic.
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- 18 Jul, 2017 1 commit
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Lucas Russo authored
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- 12 Jul, 2017 2 commits
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Lucas Russo authored
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Lucas Russo authored
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- 10 Jul, 2017 2 commits
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Lucas Russo authored
Even though we don't have much CORDIC iterations to yield a good resolution, it's good to be able to acquire the phase for debugging purposes.
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Lucas Russo authored
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- 04 Jul, 2017 1 commit
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Lucas Russo authored
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- 27 Jun, 2017 2 commits
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Lucas Russo authored
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Lucas Russo authored
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- 22 Jun, 2017 1 commit
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Lucas Russo authored
This is a more semantic name.
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- 20 Jun, 2017 4 commits
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
This will use the Sirius Booster DDS tables which differ from Storage ring slightly.
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Lucas Russo authored
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- 19 Jun, 2017 5 commits
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
This synthesis profile changes the DDS frequency table used in position_calc_core
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- 15 Jun, 2017 2 commits
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Lucas Russo authored
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Lucas Russo authored
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- 14 Jun, 2017 1 commit
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Lucas Russo authored
This fixes #68 github issue
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- 13 Jun, 2017 2 commits
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Lucas Russo authored
On outputting '1' to trigger, we must drive the FPGA iobuf to '0', as this means output to FPGA. The same for outputting '0' to trigger. Note that we use the direction pin as data so as to implement a wired-OR logic.
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Lucas Russo authored
This is important as some acquisition modes (e.g., triggered) may leave dirty buffers along the way. So, we flush all of this on each new acquisition.
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- 12 Jun, 2017 3 commits
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Lucas Russo authored
This reverts commit 7789ba36.
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Lucas Russo authored
This avoids having old parameters set by a previous acquisition.
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Lucas Russo authored
Instead of comparing to the byte sized pre/full packet we should be comparing transmitted words.
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- 09 Jun, 2017 2 commits
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Lucas Russo authored
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Lucas Russo authored
This is safer as we could have some "old" data fro a previous acquisition in the AXI datamover or AXI interconnect buffers. This would concatenate with the new data.
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- 08 Jun, 2017 1 commit
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Lucas Russo authored
The received init/end DDR address are already in bytes. So, we don't want to shift it again.
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- 07 Jun, 2017 3 commits
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Lucas Russo authored
Previously we were relying on the calculated full BTT value to be always '1' at the LSBs, but there are cases in which this is not true: 1<0000000>. This would be cropped to 0, but instead we would want the clip to the maximum BTT value.
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Lucas Russo authored
On long running acquisitions, BTT was not reseting to the maximum permitted to the memory region, so only the first pass would succeed.
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Lucas Russo authored
Previously, we were always setting the BTT as 2^22. If we needed to finish early, we just ended the transaction with TLAST. This posed a problem for long-running acquisition (triggered), in that the AXI datamover would continue to write even after the memory region, because the BTT was set to 2^22. Now, we always set it to the maximum of the memory region.
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- 06 Jun, 2017 1 commit
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Lucas Russo authored
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