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Beam Positoning Monitor - Gateware
Commit 3150cb55 authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'devel'

parents ecda1dde ee59e14b
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Showing with 721 additions and 358 deletions
dsp-cores @ 96dc9714
Subproject commit f17f5472d49446ae07c4bc2e170effde7726ba81
Subproject commit 96dc9714b14e015853f35c504b927b0e3e322db8
hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd
View file @ 3150cb55
......@@ -220,6 +220,8 @@ architecture rtl of wb_acq_core is
constant c_p2l_with_pulse2level : t_acq_bool_array(c_p2l_num_inputs-1 downto 0) :=
(false, true, true, false, true, true);
constant c_acq_start_fs_rst_pulse_width : natural := 16;
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
......@@ -269,6 +271,13 @@ architecture rtl of wb_acq_core is
signal acq_start : std_logic;
signal acq_start_sync_ext : std_logic;
signal acq_start_sync_fs : std_logic;
signal acq_start_rst : std_logic;
signal acq_start_pp_fs_sync : std_logic;
signal acq_start_rst_fs_sync : std_logic;
signal acq_start_rst_ext_sync : std_logic;
signal acq_start_rstn_fs_sync : std_logic;
signal acq_start_rstn_ext_sync : std_logic;
signal acq_start_safe : std_logic;
signal acq_now : std_logic;
signal acq_stop : std_logic;
signal acq_end : std_logic;
......@@ -445,8 +454,8 @@ begin
report "[wb_acq_core] Only g_acq_num_channels less or equal 24 is supported!"
severity Failure;
fs_rst_n <= fs_rst_n_i and acq_fsm_rstn_fs_sync;
ext_rst_n <= ext_rst_n_i and acq_fsm_rstn_ext_sync;
fs_rst_n <= fs_rst_n_i and acq_fsm_rstn_fs_sync and acq_start_rstn_fs_sync;
ext_rst_n <= ext_rst_n_i and acq_fsm_rstn_ext_sync and acq_start_rstn_ext_sync;
-----------------------------
-- Slave adapter for Wishbone Register Interface
......@@ -722,7 +731,7 @@ begin
acq_trig_i => acq_trig_i,
lmt_curr_chan_id_i => lmt_dtrig_chan_id,
lmt_valid_i => acq_start,
lmt_valid_i => acq_start_safe,
-----------------------------
-- Output Interface.
......@@ -756,7 +765,7 @@ begin
acq_trig_i => acq_trig_i,
lmt_curr_chan_id_i => lmt_curr_chan_id,
lmt_valid_i => acq_start,
lmt_valid_i => acq_start_safe,
-----------------------------
-- Output Interface.
......@@ -799,7 +808,7 @@ begin
dtrig_id_i => dtrig_id_in,
lmt_dtrig_chan_id_i => lmt_dtrig_chan_id,
lmt_dtrig_valid_i => acq_start,
lmt_dtrig_valid_i => acq_start_safe,
acq_data_i => acq_data_marsh(c_acq_data_width-1 downto 0),
acq_valid_i => acq_dvalid_in,
......@@ -807,7 +816,7 @@ begin
acq_trig_i => acq_trig_in,
lmt_curr_chan_id_i => lmt_curr_chan_id,
lmt_valid_i => acq_start,
lmt_valid_i => acq_start_safe,
acq_wr_en_i => acq_fsm_accepting,
acq_data_o => acq_data,
......@@ -853,7 +862,7 @@ begin
post_trig_samples_i => post_trig_samples_c,
shots_nb_i => shots_nb_c,
lmt_curr_chan_id_i => lmt_curr_chan_id,
lmt_valid_i => acq_start,
lmt_valid_i => acq_start_safe,
samples_cnt_o => samples_cnt,
-----------------------------
......@@ -976,7 +985,7 @@ begin
-- Request transaction reset as soon as possible (when all outstanding
-- transactions have been commited)
req_rst_trans_i => acq_fsm_req_rst, -- FIXME: Could this be acq_start = '1'???
req_rst_trans_i => acq_fsm_req_rst,
-- Select between multi-buffer mode and pass-through mode (data directly
-- through external module interface)
passthrough_en_i => acq_single_shot,
......@@ -994,7 +1003,7 @@ begin
-- Number of shots in this acquisition
lmt_shots_nb_i => lmt_shots_nb,
--lmt_valid_i => lmt_valid,
lmt_valid_i => acq_start,
lmt_valid_i => acq_start_safe,
fifo_fc_all_trans_done_p_o => fifo_fc_all_trans_done_p,
-- Asserted when the Acquisition FIFO is full. Data is lost when this signal is
......@@ -1022,6 +1031,64 @@ begin
dbg_shots_cnt_o => dbg_shots_cnt
);
------------------------------------------------------------------------------
-- Delayed start and modules reset
------------------------------------------------------------------------------
-- Reset all modules on each new acquisition. This is the first thing to
-- happen when we start an acquisition. After that, all modules are
-- started accordingly. This would be better described as a FSM, maybe,
-- but it works fine for now.
-- Acquisition start chain:
-- acq_start -> acq_start_safe -> acq_start_sync_ext -> acq_start_sync_fs
-- Extend acq_start to function as a reset to all modules
cmp_acq_start_rst_extended : gc_extend_pulse
generic map (
g_width => c_acq_start_fs_rst_pulse_width
)
port map(
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
pulse_i => acq_start,
extended_o => acq_start_rst
);
-- Sync and pipeline reset signals
cmp_reset_fs_synch : reset_synch
port map(
clk_i => fs_clk_i,
arst_n_i => acq_start_rst,
rst_n_o => acq_start_rst_fs_sync
);
cmp_reset_ext_synch : reset_synch
port map(
clk_i => ext_clk_i,
arst_n_i => acq_start_rst,
rst_n_o => acq_start_rst_ext_sync
);
acq_start_rstn_fs_sync <= not(acq_start_rst_fs_sync);
acq_start_rstn_ext_sync <= not(acq_start_rst_ext_sync);
-- Use the negative edge of the extended pulse to trigger the acq_start
-- and start all modules.
cmp_edge_detector : gc_sync_ffs
generic map(
g_sync_edge => "positive")
port map(
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
data_i => acq_start_rst_fs_sync,
synced_o => open,
npulse_o => acq_start_pp_fs_sync,
ppulse_o => open
);
acq_start_safe <= acq_start_pp_fs_sync;
------------------------------------------------------------------------------
-- Pulse to Level and Synchronizer circuits
------------------------------------------------------------------------------
......@@ -1074,7 +1141,7 @@ begin
p2l_clk_out(c_p2l_acq_start_idx) <= ext_clk_i;
p2l_rst_out_n(c_p2l_acq_start_idx) <= ext_rst_n;
p2l_pulse(c_p2l_acq_start_idx) <= acq_start;
p2l_pulse(c_p2l_acq_start_idx) <= acq_start_safe;
p2l_clr(c_p2l_acq_start_idx) <= '0'; -- not used
acq_start_sync_ext <= p2l_pulse_synched(c_p2l_acq_start_idx);
......@@ -1102,7 +1169,7 @@ begin
ddr3_all_trans_done_l <= p2l_level_synched(c_p2l_ddr3_all_trans_done_idx);
-- FIXME: We use the additional latency introduced by the conversion circuits
-- acq_start -> acq_start_sync_ext -> acq_start_sync_fs to give time to modules
-- acq_start -> acq_start_safe -> acq_start_sync_ext -> acq_start_sync_fs to give time to modules
-- downstream (acq_ddr_iface and the ones clocked by ext_clk_i) to configure
-- themselves before starting the actual acquisition. Without this, the modules
-- can misbehave as the number of samples would not be correctly set, for
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
View file @ 3150cb55
......@@ -1427,8 +1427,8 @@ begin
-- External hardware trigger synchronization
cmp_trig_sync : gc_ext_pulse_sync
generic map(
g_min_pulse_width => 1, -- clk_i ticks
--g_clk_frequency => 1/g_adc_clk_period_values(g_ref_clk), -- MHz
-- minimum pulse in ns to accept input (must be >1 clk_i ns)
g_min_pulse_width => 16,
g_clk_frequency => 130, -- MHz
g_output_polarity => '0', -- positive pulse
g_output_retrig => false,
......
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd
View file @ 3150cb55
......@@ -1539,8 +1539,8 @@ begin
-- External hardware trigger synchronization
cmp_trig_sync : gc_ext_pulse_sync
generic map(
g_min_pulse_width => 1, -- clk_i ticks
--g_clk_frequency => 1/g_adc_clk_period_values(g_ref_clk), -- MHz
-- minimum pulse in ns to accept input (must be >1 clk_i ns)
g_min_pulse_width => 8,
g_clk_frequency => 250, -- MHz
g_output_polarity => '0', -- positive pulse
g_output_retrig => false,
......
hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ 3150cb55
......@@ -1485,7 +1485,7 @@ begin
-- Trigger buffers and Synchronization
cmp_ext_trig_ibufds : ibufds
generic map(
IOSTANDARD => "LVDS_25",
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map (
......@@ -1497,8 +1497,9 @@ begin
-- External hardware trigger synchronization
cmp_trig_sync : gc_ext_pulse_sync
generic map(
g_min_pulse_width => 1, -- clk_i ticks
g_clk_frequency => 100, -- MHz
-- minimum pulse in ns to accept input (must be >1 clk_i ns)
g_min_pulse_width => 8,
g_clk_frequency => 250, -- MHz
g_output_polarity => '0', -- positive pulse
g_output_retrig => false,
g_output_length => 1 -- clk_i tick
......
hdl/modules/dbe_wishbone/wb_trigger_iface/wb_trigger_iface.vhd
View file @ 3150cb55
......@@ -145,6 +145,10 @@ architecture rtl of wb_trigger_iface is
constant c_max_num_channels : natural := 24;
-- Trigger direction constants
constant c_trig_dir_fpga_input : std_logic := '1';
constant c_trig_dir_fpga_output : std_logic := not (c_trig_dir_fpga_input);
-----------
--Signals--
-----------
......@@ -173,13 +177,23 @@ architecture rtl of wb_trigger_iface is
signal ch_regs_out : t_wb_trig_out_array(c_max_num_channels-1 downto 0);
signal ch_regs_in : t_wb_trig_in_array(c_max_num_channels-1 downto 0);
signal extended_rcv : std_logic_vector(g_trig_num-1 downto 0);
signal extended_rcv : std_logic_vector(g_trig_num-1 downto 0);
signal extended_rcv_buff : std_logic_vector(g_trig_num-1 downto 0);
signal extended_transm : std_logic_vector(g_trig_num-1 downto 0);
signal extended_transm : std_logic_vector(g_trig_num-1 downto 0);
signal rcv_pulse_bus : t_trig_channel_array(g_trig_num-1 downto 0); -- rcv pulses
signal transm_pulse_bus : t_trig_channel_array(g_trig_num-1 downto 0); -- transm pulses
signal trig_dir_int : std_logic_vector(g_trig_num-1 downto 0);
signal trig_pol_int : std_logic_vector(g_trig_num-1 downto 0);
signal trig_data_int : std_logic_vector(g_trig_num-1 downto 0);
signal trig_dir_polarized : std_logic_vector(g_trig_num-1 downto 0);
signal trig_data_polarized : std_logic_vector(g_trig_num-1 downto 0);
signal trig_dir_ext : std_logic_vector(g_trig_num-1 downto 0);
signal trig_data_ext : std_logic_vector(g_trig_num-1 downto 0);
signal trig_dir_int_buff : std_logic_vector(g_trig_num-1 downto 0);
-- signal trig_data_int_buff : std_logic_vector(g_trig_num-1 downto 0);
-- signal transm_mux_bus : std_logic_vector(g_intern_num-1 downto 0); -- input of transm multiplexers
-- signal rcv_mux_out : std_logic_vector(g_intern_num-1 downto 0);
......@@ -513,8 +527,50 @@ begin -- architecture rtl
-- Connecting signals
--------------------------------
trig_dir_o(i) <= ch_regs_out(i).ch_ctl_dir when ch_regs_out(i).ch_ctl_dir_pol = '0' else
not (ch_regs_out(i).ch_ctl_dir);
-- Implementation of wired-OR logic with trigger lines, as described
-- in www.ti.com/lit/pdf/snla113, page 11. It works as follows:
--
-- If we want to output data, we use the direction pin as data and
-- drive the actual output to HI. This would only drive the line
-- when we send data.
--
-- If we want to input data, we use the pins as usual: data as data and
-- direction as direction.
--
-- Notice that for FPGA output:
-- Direction pin 0 = Input to FPGA
-- Direction pin 1 = Output to FPGA
--
-- So, we must negate the data pin so, sending 1 will set the FPGA
-- to output ('0' in iobuf) and sending 0 will set the FPGA to input
-- ('1' in iobuf)
trig_dir_int(i) <= ch_regs_out(i).ch_ctl_dir;
trig_pol_int(i) <= ch_regs_out(i).ch_ctl_dir_pol;
trig_data_int(i) <= not (extended_transm(i));
-- Regular data/direction driving with polarity inversion
trig_dir_polarized(i) <= trig_dir_int(i) when trig_pol_int(i) = '0' else
not (trig_dir_int(i));
trig_data_polarized(i) <= trig_data_int(i) when trig_pol_int(i) = '0' else
not (trig_data_int(i));
-- Use data/direction pin as data depending if we are input or output.
-- If it's input, we just need to use the direction according to the
-- polarity ('0' means same polarity, '1' means reversed polarity).
--
-- We could have used just "not (trig_dir_int(i))" instead of trig_dir_polarized(i)
-- here, but we opted for clarity in the hope the tools will optimize this
trig_dir_ext(i) <= trig_data_polarized(i) when trig_dir_int(i) = c_trig_dir_fpga_output else
trig_dir_polarized(i);
trig_data_ext(i) <= '1' when trig_dir_int(i) = c_trig_dir_fpga_output else '0';
-- Internal buffer direction/data
trig_dir_int_buff(i) <= trig_data_int(i) when trig_dir_int(i) = c_trig_dir_fpga_output else
trig_dir_int(i);
--trig_data_int_buff(i) <= '1' when trig_dir_int(i) = c_trig_dir_fpga_output else '0';
-- Trigger direction external output
trig_dir_o(i) <= trig_dir_ext(i);
--------------------------------
-- Transmitter and Receiver Cores
......@@ -549,12 +605,12 @@ begin -- architecture rtl
port map (
o => extended_rcv_buff(i), -- Buffer output for further use
io => trig_b(i), -- inout (connect directly to top-level port)
i => extended_transm(i), -- Buffer input
t => ch_regs_out(i).ch_ctl_dir -- 3-state enable input, high=input, low=output
i => trig_data_ext(i), -- Buffer input
t => trig_dir_int_buff(i) -- 3-state enable input, high=input, low=output
);
trig_dbg_o(i) <= extended_rcv_buff(i);
extended_rcv(i) <= extended_rcv_buff(i) when ch_regs_out(i).ch_ctl_dir = '1' -- FPGA is input
extended_rcv(i) <= extended_rcv_buff(i) when trig_dir_int(i) = c_trig_dir_fpga_input
else '0'; -- FPGA is output
--------------------------------
......
hdl/syn/afc_v3/vivado/dbe_pbpm/synthesis_descriptor_pkg.vhd
View file @ 3150cb55
-- package generated automatically by gen_sdbsyn.py script --
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor_pkg is
constant c_sdb_repo_url : t_sdb_repo_url := (
repo_url => "https://github.com/lnls-dig/bpm-gw.git ");
constant c_sdb_top_syn_info : t_sdb_synthesis := (
syn_module_name => "bpm-gw+ ",
syn_commit_id => "960efc8c227ca92489e28547d5adb833",
syn_tool_name => "VIVADO ",
syn_tool_version => x"00201521",
syn_date => x"20151208",
syn_username => "LRusso ");
constant c_sdb_dsp_cores_syn_info : t_sdb_synthesis := (
syn_module_name => "dsp-cores+ ",
syn_commit_id => "befc6979e416ef28cc042b3030a8140b",
syn_tool_name => " ",
syn_tool_version => x"00000000",
syn_date => x"00000000",
syn_username => " ");
constant c_sdb_etherbone_core_syn_info : t_sdb_synthesis := (
syn_module_name => "etherbone-core ",
syn_commit_id => "b29565ac63ca92987cd9a9a754b6add8",
syn_tool_name => " ",
syn_tool_version => x"00000000",
syn_date => x"00000000",
syn_username => " ");
constant c_sdb_general_cores_syn_info : t_sdb_synthesis := (
syn_module_name => "general-cores ",
syn_commit_id => "cc53ef7f6c381ca1ce56355b2fd99246",
syn_tool_name => " ",
syn_tool_version => x"00000000",
syn_date => x"00000000",
syn_username => " ");
end package;
\ No newline at end of file
-- This file will be overwritten prior to synthesis,
-- by hdlmake "syn_pre_cmd" specified on top Manifest.py.
--
-- However, hdlmake requires all files to be present
-- on parsing-time. So, fool the tool with this dummy
-- file so we can bypass this requirement.
hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Manifest.py
View file @ 3150cb55
......@@ -3,6 +3,7 @@ target = "xilinx"
syn_device = "xc7a200t"
sim_tool = "modelsim"
top_module = "wb_acq_core_tb"
sim_top = "wb_acq_core_tb"
modules = {"local" : [
"../../../../../../modules/dbe_wishbone",
......@@ -10,19 +11,17 @@ modules = {"local" : [
"../../../../../../modules/rffe_top",
"../../../../../../modules/fabric",
"../../../../../../modules/fmc_adc_common",
# "../../../../../../modules/pcie",
"../../../../../../ip_cores/general-cores",
"../../../../../../ip_cores/etherbone-core",
"../../../../../../platform",
"../../../../../../sim",
"../../../../../../sim/ddr_model",
"../../../../../../platform/artix7/afc_v3"]}
files = ["wb_acq_core_tb.v", "axi_interconnect_wrapper.vhd", "ddr_core_wrapper.vhd", "defines.v", "timescale.v",
files = ["wb_acq_core_tb.v", "axi_interconnect_wrapper.vhd", "ddr_core_wrapper.vhd",
"clk_rst.v", "../../../../../../sim/wishbone_test_master.v",
"../../../../../../../../../../../opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v"]
"/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v"]
include_dirs = ["../../../../../../sim", "../../../../../../sim/regs", "../../../../../../sim/ddr_model",
"../../../../../../platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog"]
include_dirs = ["../../../../../../sim", "../../../../../../sim/regs", "../../../../../../sim/ddr_model/artix7",
"../../../../../../platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog", "."]
vlog_opt = "+incdir+../../../../../../sim/regs +incdir+../../../../../../sim +incdir+../../../../../../sim/ddr_model +incdir+../../../../../../platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog"
vlog_opt = "+incdir+../../../../../../sim/regs +incdir+../../../../../../sim +incdir+../../../../../../sim/ddr_model/artix7 +incdir+../../../../../../platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog +incdir+."
hdl/top/afc_v3/vivado/dbe_bpm/dbe_bpm.xdc
View file @ 3150cb55
......@@ -1141,8 +1141,10 @@ set_multicycle_path 7 -hold -from [all_fanout -endpoints_only -only_cells -from
## Bitstream Settings ##
#######################################################################
#set_property BITSTREAM.Config.SPI_BUSWIDTH 1 [current_design]
#set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 12 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
hdl/top/afc_v3/vivado/dbe_bpm2/dbe_bpm2.xdc
View file @ 3150cb55
......@@ -1306,9 +1306,10 @@ set_multicycle_path 7 -hold -from [all_fanout -endpoints_only -only_cells -from
## Bitstream Settings ##
#######################################################################
#set_property BITSTREAM.Config.SPI_BUSWIDTH 1 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 12 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.xdc
View file @ 3150cb55
......@@ -523,9 +523,10 @@ set_multicycle_path 7 -hold -from [all_fanout -endpoints_only -only_cells -from
## Bitstream Settings ##
#######################################################################
#set_property BITSTREAM.Config.SPI_BUSWIDTH 1 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 12 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
hdl/top/afc_v3/vivado/test_trigger/transm/Manifest.py
View file @ 3150cb55
......@@ -2,8 +2,7 @@ files = [ "test_trigger_transm.vhd",
"sm_transm.vhd",
"sys_pll.vhd",
"clk_gen.vhd",
"extend_pulse_dyn.vhd"
"test_trigger_transm.xcd"];
"test_trigger_transm.xdc"];
modules = { "local" :
["../../../../.."]
......
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