Remove voltage translators for the M-LVDS inputs
MLVDS circuit could be simplyfied by using the separate receiver/driver signals from the M-LVDS and using different pins for input and output in the FPGA. This would remove the need for bus direction selection, and the FPGA gateware can just ignore the inputs when transmitting in the channel.
In this manner, we could employ the 8-bit SN65MLVD082 (or 080 for Type-1 receiver), allowing for better skew between channels (350ps, before it was 800ps), specially in the reception, as the voltage translation from the 3.3V M-LVDS driver to the 1.5V bank could be done by using only resistors and/or fast diodes.
The output would still need a voltage translator, but this can be unidirectional and do not need to be controlled by the FPGA. NXP 74AVC8T245 has 8 channels and allow for data rates above 200Mbps in this application. To avoid glitching the bus while programming, this translator OE could be set up as proposed in issue #87 (closed).
This would also simplify schematics, and the faster transition between receiving and sending could allow for better reuse of the bus for trigger signaling. And this modification would not need demand more pins in the FPGA. The main downside would be the lost of the ability to switch between Type 1 and Type 2 receivers dinamically, as the 8-pin MLVDS options have only one receiver option.