Implement DESY's RTM D1.3 pinout

To allow the board to be used with a wider array of RTMs, it is necessary to try to follow the industry standard.

From Tomazs suggestion:
Missing LVDS lines can be muxed with the HA/HB lines of one of the FMCs using a passive multiplexer. The RTM will still need
the same Vadj as the mezzanine, though...

assigned to @tprzywoz

changed milestone to %AFC v4.0

The pin multiplexing could be done entirely by assembly variants in order to reduce complexity and avoid special circuitry like level translators between the RTM connector and the FPGA.

I propose a rather radical change on the RTM pin assignment where all 28 LVDS pairs which are required by DESY's D1.3 pinout are connected, at the expense of downgrading one FMC slot from HPC to LPC. This seems a fair price to be paid to have a fully populated RTM with all the flexibility the FPGA I/Os can offer.

In order to comply with the D1.3 pinout, there should be 3 I/O banks associated with the RTM I/O pins. The third RTM I/O bank has only 4 pins (J31 7ab and J31 8ab) and this may be included in the 2nd bank being slightly out of spec.

Ideally the FPGA I/O banks 12 and 15 power supply should be independent from the FMC Vadj.

The final proposal is the following:

Bank 12 in the FPGA

• RTM J30 connector (AFC J1)
  • row 3 from e to f
  • row 4 from c to f
  • row 5 from a to f
  • row 6 from a to f
  • row 7 from a to f
  • row 8 from a to f

Bank 15 in the FPGA

• RTM J30 connector (AFC J1)
  • row 9 from a to f
  • row 10 from a to f
• RTM J31 connector (AFC J2)
  • row 1 from a to f
  • row 2 from a to f
  • row 3 from a to b
  • row 4 from a to b
  • row 7 from a to b
  • row 8 from a to b

mentioned in issue #103 (closed)

Solved in d2255c95

closed

Important note: In current design, only FMC2 with LPC connector can be used parallel to RTM.

Do you mean LPC pin assignment on FMC2? Or truly the need of mounting the LPC connector instead of HPC connector?

It means once the option for the LPC on FMC2 is made, there's no easy way to revert it by remounting the resistors. Is this what you mean? This "price to be paid" still seems acceptable to me. Not sure what other users would say...

If RTM jumpers (resistors 0) are mounted we must use true LPC connector. Without them (and after mounting some FMC jumpers) we can use full HPC.

I can anticipate only one real issue here. We'll loose the option to have LPC + 4 MGTs on FMC2, as we discussed in #124 (closed), since the additional 3 transceiver ports (DP1-DP3) are only available on HPC connectors.

The only drawback I see by making this way is that users won't be able to have HA and HB FMC banks plus 4 MGTs on FMC slot when RTM with MGT is in use. They will have to choose among FMC1 with HPC and no MGT or FMC2 LPC + 4 MGTs. This should be no big issue however, since many FMCs requiring MGTs do not make use of many I/O pins.

If there's still room/time for this, I propose FMC2 DP0 port is multiplexed with the last RTM port via assembly option, that is, RTM_GTP7 (it is currently mux'ed with GTP5). If possible, multiplex with AMC P2P port 15 too (currently port 12).

When using FMC2 LPC+RTM (only DP0 on FMC2) some users could still want to have the single FMC MGT affecting the rest of the GTPs the least.

reopened

We've agreed with @tprzywoz that this can be constrained by the layout. If it won't cause a chain reaction leading to major layout rework in that area we can do it.

@tprzywoz you did not include it due to layout constraints or it was just missed?

changed milestone to %AFC v4.1

We assumed it would take too long to implement such swap for 4.0.

removed milestone

OK, issue closed.

closed