MMC JTAG/SWD cable can't be used when P3V3 is off and the AFC is inserted in the crate

When P3V3 is off, the IC46 connects the AMC_TDI/TDO/TCK/TMS JTAG signals to MMC_TDI/TDO/TCK/TMS preventing an external debugger from accessing the MMC microcontroller through J9.

To fix it, the IC46 OE signal must be driven low high when P3V3 is off and J9 is connected.

changed milestone to %AFC v4.0

changed the description

changed milestone to %AFC v4.0.2

@augustofg are you sure about this:

To fix it, the IC46 OE signal must be driven low when P3V3 is off

I think that when P3V3 is off T7 keeps OE low.

My mistake, it should be held high when the MMC JTAG/SWD/ETM connector (J9) is connected if P3V3 is low. To make things clearer:

P3V3	J6	J9	OE	Comments
OFF	X	Disconnected	Low	MMC JTAG connected to AMC_*
OFF	X	Connected	High	MMC JTAG connected to a debugger through J9
ON	Disconnected	X	Low	FPGA JTAG connected to AMC_*
ON	Connected	X	High	FPGA JTAG connected to a interface through J6

Edit: swap J6 for J9

This is preliminary proposition. I added T1, T2, D33, C595, R449. @augustofg what do you think abou it?

It is not correct, when P3V3 is OFF and JTAG_MMC_presence is low T2 won't conduct, T7 will conduct and OE will be low (enabled).

changed the description

Sorry, I haven't realized that when P3V3 is off it can't power transistor and PU. Anyway, by "X" in table you mean that JTAG cable is absent?

Ok, this transistor logic is tricky to get right. By X I mean 'don't care'.

It would be a good idea to write a text note explaining the JTAG switching logic to avoid confusion when reading the schematic.

In the table you posted before, first two rows are how it is now. And next two, are to implement. They are dependent from J9, but it seems that when you would like this:

it (OE) should be held high when the MMC JTAG/SWD/ETM connector (J9) is connected if P3V3 is low

then you have to plug in J6...I can try to make this logic but I'm not sure if it is what it should be.

Don't you want something like this?

P3V3	J6	J9	OE	Comments
OFF	X	Disconnected	Low	MMC JTAG connected to AMC_*
OFF	X	Connected	High	MMC JTAG connected to a debugger through J9
ON	Disconnected	X	Low	FPGA JTAG connected to AMC_*
ON	Connected	X	High	FPGA JTAG connected to a interface through J6

You are right @Filip.Switakowski. I swapped J6 for J9.

So I changed Pu T7 to P3V3. T2 should turn off T1 when P3V3 is presense. I think this should cover this table.

It seems OK now.

mentioned in issue #188 (closed)

closed