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gc argb led drv
general-cores!67
· created
May 03, 2024
by
Tristan Gingold
Merged
0
updated
May 03, 2024
Add macro-based dpram for Xilinx/AMD 7Series FPGA
general-cores!66
· created
May 02, 2024
by
Frederik Pfautsch (MLE)
Merged
0
updated
May 03, 2024
dev/simple-uart.c: Implement missing purge functions
wrpc-sw!18
· created
May 02, 2024
by
Frederik Pfautsch (MLE)
wrpc-v5
Merged
0
updated
Jul 15, 2024
modules/wrc_core/wrc_periph: I2C HIGH init value
wr-cores!13
· created
May 02, 2024
by
Frederik Pfautsch (MLE)
wrpc-v5
Closed
3
updated
Jun 17, 2024
Addition of board specific OID that we need to control the timing output of the…
wrpc-sw!17
· created
Apr 29, 2024
by
Konstantinos Asteriou
wrpc-v5
Merged
0
updated
May 15, 2024
add -min argument to get_property PERIOD to return the minimum value of the returned list
general-cores!65
· created
Apr 16, 2024
by
Julien Egli
Merged
0
updated
Apr 16, 2024
fix snmp sfp dom accuracy
wr-switch-sw!5
· created
Mar 19, 2024
by
Fabian Mauchle
bug
0
updated
Mar 19, 2024
preserve dot-config during firmware upgrade
wr-switch-sw!4
· created
Mar 12, 2024
by
Fabian Mauchle
0
updated
Mar 12, 2024
WIP: Resolve "Use Verible for Verilog formatting"
urv-core!4
· created
Feb 12, 2024
by
Shareef Jalloq
0
WIP: Resolve "Bug: register x0 should be hardwired to zero"
urv-core!3
· created
Feb 12, 2024
by
Shareef Jalloq
0
updated
Feb 12, 2024
Resolve "Would you be happy to integrate FuseSoC core files into the repo?"
urv-core!2
· created
Feb 07, 2024
by
Shareef Jalloq
Merged
1
updated
Feb 12, 2024
Resolve "Support Verilog output with gen_sourceid tool"
general-cores!63
· created
Jan 30, 2024
by
Dimitris Lampridis
Merged
1
updated
Jan 30, 2024
Option to include .mk at end of generated Makefile
hdl-make!30
· created
Jan 25, 2024
by
Istvan Kiss
develop
0
updated
Jan 25, 2024
Add support for legacy LiberoSoC 11.9 as separate tool file, ProASIC3 support; rebased onto latest Develop branch
hdl-make!29
· created
Jan 24, 2024
by
Istvan Kiss
develop
6
updated
Jan 25, 2024
Resolve "Linux driver for wb simple uart"
general-cores!62
· created
Jan 24, 2024
by
Konstantinos Blantos
software
Merged
0
updated
Mar 11, 2024
Resolve "possible_fix_in_wb_uart_rx_fifo"
general-cores!61
· created
Jan 23, 2024
by
Konstantinos Blantos
Closed
0
updated
Jan 26, 2024
Create branch wb_axi_bridge_fix and add fix for wb - axi4 lite bridge
general-cores!60
· created
Jan 23, 2024
by
Quentin Genoud
Merged
0
updated
Jan 23, 2024
WIP: Resolve "inferred_async_fifo_dual_reset : spurious pulse on almost_full_int after reset"
general-cores!59
· created
Jan 22, 2024
by
Alexis Marquet
0
updated
Jan 22, 2024
NVC: Add new variables for setting analysis and elaboration flags, update documentation
hdl-make!28
· created
Jan 19, 2024
by
Augusto Fraga Giachero
develop
Merged
0
updated
Jan 25, 2024
Add support to NVC simulator
hdl-make!27
· created
Jan 16, 2024
by
Augusto Fraga Giachero
develop
Merged
1
updated
Jan 17, 2024
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