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Power supply
3 of 3 tasks completed
svec7#9
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
7
updated
Mar 23, 2020
Slow I/O
svec7#8
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Feb 19, 2020
Flash memory
svec7#6
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Mar 01, 2020
Change the DDR memory to a DDR SO-DIMM module socket (no ECC)
svec7#5
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Feb 19, 2020
Remove the discrete DDR chips (IC28, IC4)
svec7#4
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Feb 10, 2020
Remove J1 and J16 (stand-alone power port)
svec7#3
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Jul 02, 2020
Change the FPGA to XC7K160T-2FBG676
svec7#1
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Feb 25, 2020
Replace ADCLK925 with LTC6957-2
wr2rf-vme#44
· opened
Jun 29, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
18
updated
Jul 08, 2020
Missing correct symbols in rf_main sheet
wr2rf-vme#43
· opened
Jun 12, 2020
by
Mattia Rizzi
Schematic done
critical
hw
CLOSED
1
updated
Jun 12, 2020
DAC clock - AC coupling
wr2rf-vme#32
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
critical
hw
CLOSED
9
updated
Jun 30, 2020
pulse shaper - vcc connected to vin
wr2rf-vme#20
· opened
May 12, 2020
by
Tristan Gingold
Schematic done
critical
hw
CLOSED
1
updated
May 12, 2020
Replace capacitors and inductors with proper symbols in RF main sheet
wr2rf-vme#9
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
4
updated
Jun 18, 2020
Verify that the BE-RF VME crate power supplies can deliver enough current on P1
wr2rf-vme#4
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
26
updated
Jul 07, 2020
IRLML2803PBF must be replaced with PMV40UN2R
wr2rf-vme#2
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
2
updated
Feb 05, 2021
Use separate FPGA pins for the two WR EEPROMs
wr2rf-vme#40
· opened
May 19, 2020
by
Dimitris Lampridis
Schematic done
hdl
hw
important
xdc update
CLOSED
3
updated
Jun 29, 2020
delay line for TU
wr2rf-vme#39
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
CLOSED
3
updated
Jun 25, 2020
Power sequencing and consumption
wr2rf-vme#37
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
7
updated
Jun 29, 2020
Dielectric of ceramic capacitors in the RF path
wr2rf-vme#34
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
important
CLOSED
3
updated
Jun 10, 2020
DC coupling for FPGA clock ECL to LVDS
wr2rf-vme#31
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
5
updated
Jun 25, 2020
Trigger unit output glitches
wr2rf-vme#30
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
9
updated
Jun 16, 2020
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