delay line for TU
The power consumption is quite an issue. The output delay line are a big consumer in the design.
The alternative chip NB6L295 can be an option at a price of reduce delay range (5.7ns instead of 10.4ns typ). The power consumption will be then divided by almost 2. I guess The added jitter will be negligeable .
The control is a serial link and will reduced the number of IO of the FPGA. Enable signal is TTL. So this will also remove the adaptation TTL->ECL