Power sequencing and consumption
the DC/DC LMZ317 do not have the soft-start function used. Might be good to sync the multiple device together and ramp the output voltage. I do not see that all FPGA power supply sequencing. Two DC/DC sources the LDO's may need to be synchronized (ramp-up). I would power-up all LDO's at the same time for symplicity. What is the strategy behing? The routing will be very complex, powering simplification may help.
The P1V8 and P1V8_VCCO can be merged (removes one LDO). The P3V3 and P3V3_VCCO can be merged (removes one LDO).
In the power budget file, no distinction of the P1V0 and P1V0_GTX
I do not find the source of the P3V3_PLL.
20mA for P3V3_VCCO seems too low.
The pecl consumption seem to be over estimated. for example the ADCLK925, the ICC max is 97mA, but IEE=51mA, there is 46mA diff, where does it go? I can only imagine it is for output current. So I guess we should not add 28mA per output again (Y termination). You will gain few hundreds of mA here. Maybe same comment for the other ECL devices?
For trigger units: you use two ADCLK925 in cascade with power comsumption of 97mA each. if you use the ADCLK944, you gain 20mA and it may simplify the routing and reduce PCB area. At the cost of one ref in the bom.
Is it necessary to use three LDOs for 1.0V? why not generting directly the P1V0 with the DC/DC? it will save 3 chips and 1.5W. The GTX is for 1.23GSPS White-rabbit so I guess it is not the most critical gbits link. 30% of power. we could merge the P1V0_GTX ith P1V0? (only one LDO and ferrites beads for GTX power)
I put a tentative simplification of the powering scheme, to be discussed if good idea (or not at all ;)review_powering.pdf