Commits · 4c7d3f56ebc1b272fbbf99991d7a6bfc2bb1c8b7 · fmc-projects / fmc-tdc / fmc-tdc-1ns-5cha-gw · GitLab

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Dec 11, 2017
- top/svec: cleanup indentation and remove unused signals · 4c7d3f56
  Grzegorz Daniluk authored 7 years ago
  
  4c7d3f56
- top/svec: reorganized to use WRPC Board wrapper · 6185eb76
  Grzegorz Daniluk authored 7 years ago
  
  6185eb76
- update wr-cores · e665f6c1
  Grzegorz Daniluk authored 7 years ago
  
  e665f6c1
- top/spec: cleanup, ports rename · 48f0a742
  Grzegorz Daniluk authored 7 years ago
  
  48f0a742
- adding etherbone submodule (needed for WR board wrapper) · 98bb71d9
  Grzegorz Daniluk authored 7 years ago
  
  98bb71d9
- update vme64x-core to the latest one by Tristan · 86a9d895
  Grzegorz Daniluk authored 7 years ago
  
  86a9d895
- svec: vme ports to lower case · 5ee897b8
  Grzegorz Daniluk authored 7 years ago
  
  5ee897b8
- update general-cores to match wr-cores v4.2rc · 269cc7d1
  Grzegorz Daniluk authored 7 years ago
  
  269cc7d1
- update wr-cores to the latest proposed_master · 52395a8e
  Grzegorz Daniluk authored 7 years ago
  
  52395a8e
- svec: output 1-PPS to LEMO · e49fb3dc
  Grzegorz Daniluk authored 7 years ago
  
  e49fb3dc
- svec_tdc: add SPI Flash and 1-PPS out signals · 6b5e46a8
  Grzegorz Daniluk authored 7 years ago
  
  6b5e46a8
- Uploaded v7.0 sources with wrpc v 4.1 · 572973e6
  Tomasz Wlostowski authored 7 years ago and Grzegorz Daniluk committed 7 years ago
  
  572973e6
- fmc_tdc_core: decrease timestamp FIFO size to 512 (so that it fits in the SPEC with WPRC v4.1) · d4e10faf
  Tomasz Wlostowski authored 7 years ago and Grzegorz Daniluk committed 7 years ago
  
  d4e10faf
Mar 08, 2017
- update wrc.ram for spec to fix DAC range problem on some SPECs · b2433b14
  Grzegorz Daniluk authored 8 years ago
  
  b2433b14
Jan 17, 2017
- include WRPC LM32 firmware v2.1 for SVEC · 7b2bad61
  Evangelia Gousiou authored 8 years ago
  
  7b2bad61
- include WRPC LM32 firmware v2.1 · 8597e333
  Grzegorz Daniluk authored 8 years ago
  
  8597e333
- adding Xilinx ISE project file for SPEC · 4d681a60
  Grzegorz Daniluk authored 8 years ago
  
  4d681a60
- update gennum core version · 1170651f
  Grzegorz Daniluk authored 8 years ago
  
  1170651f
May 22, 2015
- top: updated synthesis descriptors · 3b60a1ec
  Tomasz Wlostowski authored 9 years ago
  
  3b60a1ec
May 19, 2015
- hdl: SPEC top level with refurbished TDC core · 5765c94d
  Tomasz Wlostowski authored 9 years ago
  
  5765c94d
May 18, 2015
- top/spec: removed non-WR top level · caaf87ad
  Tomasz Wlostowski authored 9 years ago
  
  caaf87ad
Apr 29, 2015
- hdl: independent FIFO buffers per channel - top level verified on the SVEC · c2a10e64
  Tomasz Wlostowski authored 9 years ago
  
  c2a10e64
Apr 14, 2015
- first version with per-channel FIFOs instead of a shared circular buffer · 8b800231
  Tomasz Wlostowski authored 9 years ago
  
  8b800231
Apr 10, 2015
- fmc_tdc_wrapper: squeezed direct readout into 64kB address range · 4e08d33b
  Tomasz Wlostowski authored 9 years ago
  
  4e08d33b
- hdl/syn/svec: added missing Manifest file · 8600d4e2
  Tomasz Wlostowski authored 9 years ago
  
  8600d4e2
- hdl: use proposed_master of general-cores · 5ae41634
  Tomasz Wlostowski authored 9 years ago
  
  5ae41634
Apr 09, 2015
- hdl: various fixes: · d23de3f5
  Tomasz Wlostowski authored 9 years ago
```
- squeezed A24 address range to 0.5 MB (to fit a full 24-slot VME crate with TDCs)
- fixed IRQ line synchronization issue
```
  d23de3f5
- hdl/ip_cores: use latest VME core · 35b478e1
  Tomasz Wlostowski authored 9 years ago
  
  35b478e1
Apr 03, 2015
- top/svec: single, WR-only top level · 92b7f5e7
  Tomasz Wlostowski authored 9 years ago
  
  92b7f5e7
Mar 26, 2015
- fixed .gitignore · 3ee4e288
  Tomasz Wlostowski authored 9 years ago
  
  3ee4e288
- testbench: sample top level testbench for SVEC · 389734e7
  Tomasz Wlostowski authored 9 years ago
  
  389734e7
- top/svec: single system-clock synchronous version for the SVEC carrier, removed no-WR top level · b358b1ed
  Tomasz Wlostowski authored 9 years ago
  
  b358b1ed
- rtl: compile fixes for system-clock synchronous redesign of the core · 6fbfbd34
  Tomasz Wlostowski authored 9 years ago
  
  6fbfbd34
- rtl: moved full mezzanine wrapper code & direct readout module to the core sources directory · 5f48c026
  Tomasz Wlostowski authored 9 years ago
  
  5f48c026
Mar 25, 2015
- fmc_tdc_wrapper: no need for cross-clocking IRQ signal after clock tree rewrite · 2d00d3ef
  Tomasz Wlostowski authored 9 years ago
  
  2d00d3ef
- rtl: rewrote circular_buffer to use generic RAM instead of an NGC · 22139218
  Tomasz Wlostowski authored 9 years ago
  
  22139218
Mar 20, 2015
- hdl: added OHWL repos as Git submodules. Removed .ngc cores (will replace with genrams) · 9e39ab1f
  Tomasz Wlostowski authored 9 years ago
  
  9e39ab1f
- removed all old IP cores, will switch to git submodules · fa16e238
  Tomasz Wlostowski authored 9 years ago
  
  fa16e238
- merged clock tree fixes branch · bf36a0c8
  Tomasz Wlostowski authored 9 years ago
  
  bf36a0c8
- move hdl one dir up · 4d472dcb
  Tomasz Wlostowski authored 9 years ago
  
  4d472dcb