hdl: added OHWL repos as Git submodules. Removed .ngc cores (will replace with genrams)

.gitmodules

+[submodule "ip-cores/general-cores"]
+	path = hdl/ip_cores/general-cores
+	url = git://ohwr.org/hdl-core-lib/general-cores.git
+[submodule "hdl/ip_cores/wr-cores"]
+	path = hdl/ip_cores/wr-cores
+	url = git://ohwr.org/hdl-core-lib/wr-cores.git
+[submodule "hdl/ip_cores/vme64x-core"]
+	path = hdl/ip_cores/vme64x-core
+	url = git://ohwr.org/hdl-core-lib/vme64x-core.git
+[submodule "hdl/ip_cores/gn4124-core"]
+	path = hdl/ip_cores/gn4124-core
+	url = git://ohwr.org/hdl-core-lib/gn4124-core.git

general-cores @ 97bc7197

+Subproject commit 97bc71975252b32cf8a47ba895f7010734f015e5

gn4124-core @ e0dcb3f9

+Subproject commit e0dcb3f9a3e6804f64c544743bdf46b5fcbbefab

vme64x-core @ aa37242a

+Subproject commit aa37242a6ef7a317360fe730cf349d1cdf02ac9a

wr-cores @ 598a2f6c

+Subproject commit 598a2f6ccbf1ac937ff589c0797cd2a487306efe

hdl/platform/xilinx/Manifest.py

-files = [
-    "blk_mem_circ_buff_v6_4.ngc",
-    "blk_mem_gen_v6_1.ngc",
-    "blk_mem_gen_v6_2.ngc",
-    "blk_mem_gen_v6_3.ngc",
-    "Manifest.py"
-]