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Production and functional tests for PXIe controller COM Express based. More info at the Wiki page

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

A software suite written in Python to help with production tests of PCBs. AKA PTS.

Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.

A VHDL core for a PCI slave. The other side behaves like a Wishbone master.

More info at the Wiki page

A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page

A low cost, low complexity FMC carrier based on Xilinx Artix-7