P
PCI core
A VHDL core for a PCI slave. The other side behaves like a Wishbone master.
More info at the Wiki page
Project ID: 10873
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Michael Reese authoredb9a237ef
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A VHDL core for a PCI slave. The other side behaves like a Wishbone master.
More info at the Wiki pageName |
Last commit
|
Last update |
---|---|---|
doc | Loading commit data... | |
src | Loading commit data... | |
Manifest.py | Loading commit data... | |
README | Loading commit data... |