Explore projects
-
A VME card that is used to recover RF, bunch and revolution clocks over a white rabbit network.
Updated -
Tool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
Updated -
This project contains all the HDL gateware necessary for the FPGA of the WR switch.
Updated -
Distribution of clock signals over a White Rabbit network. It uses an PLL with a numerically controlled (DDS) oscillator to extract the characteristics of a signal that in turn are distributed over a White Rabbit network to receiving nodes with a DAC that regenerate exactly the same signal in phase. More info at the Wiki page
Updated -
Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page
Updated -
Couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP. More info at the Wiki page
Updated -
-
The VFC is a VME carrier for two VITA 57 (FMC) mezzanines. For more details please refer to the wiki pages. Obsolete project. Replaced by VFC-HD.
Updated -
A fine delay generator in FMC LPC format with 1 input and 2 outputs. The resolution is 1 ns. Optimized for high frequency pulse repetition rates synchronized to an external clock. More info at the Wiki page
Updated -
Production and functional tests for fmc-dac-600m-12b-1cha-dds
Updated -
FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). More info at the Wiki page
Updated -
Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.
Updated -
A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page
Updated -
DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.
Updated -
Gateware (VHDL) for the level conversion board Conv TTL Blocking in VME64x form factor between TTL and blocking levels. More info at the Wiki page
Updated -
Gateware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.
Updated -
A low cost, low complexity FMC carrier based on Xilinx Artix-7
Updated -
The AsyncArt Project is comprised by a set of Open-Source HDL libraries and examples targeted to the efficient implementation of Globally Asynchronous, Locally Synchronous (GALS) design architectures over Commercial-Off-The-Shelf FPGA devices.
Updated -
A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
Updated -
TiCkS is a flexible White Rabbit based time-stamping board. It is based on the SPEC board developed for the CTA collaboration. It provides an interface to a CTA camera (Inputs: Read-out Trigger signals, Busy Trigger), (Outputs: PPS signal , 10MHz clock, External trigger signal).
Updated