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Software support for the SVEC board, including kernel and user-space Linux code.
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A simple VME64x carrier for two high pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Follow-up of SVEC.
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A small PCB that generates 3.3 Volt so that a SVEC can work in older type of VME crates. The SVEC is a VME64x board where usually the 3.3 Volt supply is delivered by the crate itself. Older VME types do not generate this 3.3 Volt.
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Stereo cores process a 640x480 video pair sequence and estimate depth in the scene (fixed point Q7.4) up to 32 fps. A Lucas-Kanade gradient-based and a phase-based Handel-C implementations are provided. They also include a previous calibration stage.
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SPIETBOX is a board developed around a SPARTAN-3 FPGA in order to process TTL and SSI encoders. The board is design to work in stand alone or connected to a SPICONTROLLER via the SPI interface.
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SPICONTROLLER is the controller board for the SPI Boards Package. It manage communication task with control system via Ethernet and with modular boards via SPI interface. Moreover, specific process can be embedded into the controller.
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SPI Boards Package is a set of electronic boards developed at Soleil Synchrotron (France). These boards can be connected together in a daisy chain and they communicate with an embedded controller via an SPI Bus. They provide the following features:
- Platform allowing us to build specific solutions with simple and open tools.
- Modular architecture.
- Provide solutions for applications which require synchronization.
- Low level process implementation to achieve better performance. - Easy Control network connection
The main CPU board contains a microprocessor. It manages a task for communication with the supervision, an embedded process and SPI communication with the peripheral boards. We have a modular approach that means we can make various Peripheral board combinations between 16-bit DAC, 16-bit ADC, and a calculator board for motor encoder.
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A simple 4-lane PXIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Labview driver available for Fine Delay and TDC mezzanines. More info at the Wiki page
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A simple 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Linux and Labview drivers available for some mezzanine cards. More info at the Wiki page
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Projects / Simple PCIe FMC carrier SPEC - Software
GNU General Public License v2.0 or laterSoftware support for the SPEC board, including kernel and user-space Linux code. The package also include the fmc-bus driver, which is expected to be used by other carriers as well.
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Detailed documentation on how to get ready to work with the Simple PCI Express Carrier, including hardware deployment instructions, full required toolchain setup and and a collection of step-by-step demonstrative tutorials.
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The spec-box-3n allows to use up to three SPEC FMC carriers in stand-alone mode, not plugged inside a PC. An internal 230V supply module powers the SPEC boards. The box contains fans to cool the cards. More info at the Wiki page
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The spec-box-1n allows to use a SPEC FMC carrier in stand-alone mode, not plugged inside a PC. An external 12 volt supply should be used to power the box. There is no forced ventilation in the box. More info at the Wiki page
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A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page
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A 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). SPEC carrier based with a larger FPGA. Commercially available. More info at the Wiki page
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Hardware and software (libraries and GUI) to implement the SFF-8472 standard “Diagnostic Monitoring Interface for Optical Transceivers”. The hardware implements four SFP+s that can be exercised in parallel. To access the I2C interfaces a USB to I2C chip is used. More info at the Wiki page
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SDB (Self-describing Bus) allows to enumerate the cores that are live in the current FPGA binary, either from the host computer or from the internal soft-core CPU in the FPGA itself. The project provides the software support and the specification. More info at the Wiki page
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Stand Alone Carrier with 18 FMC LPC slots based on Spartan FPGAs, mini-ITX board and ATX supply. More info at the Wiki page
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RF over Ethernet, a protocol. Based on an extension of IEEE 1914.3 - IEEE Standard for Radio over Ethernet Encapsulations and Mappings. More info at the Wiki page
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RHINO (Reconfigurable Hardware Interface for computiNg and radiO) is a compute platform consisting of a FPGA element with dedicated memory, high speed communication, and FMC-LPC (Vita 57.1) IO expansion slots, all controlled via an ARM Cortex A8 processor running the BORPH operating system.
For progress updates, follow us on twitter @rhinoplatform
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