Explore projects

The nanoFIP test board is used to test the functionality of the nanoFIP design. Apart from the nanoFIP chip, the FielDrive and the FieldTR it houses another Actel FPGA that can access nanoFIP in stand-alone or in memory mode. This FPGA can also communicate through a RS232 port with a windows PC running the NFTC software. The components on the board are placed in such a way that with a focused beam, radiation tests can be performed to the nanoFIP, FielDrive and FieldTR, leaving the rest if the components in a radiation-safe zone. The card has been designed by the company HLP.

A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.

A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available. More info at the Wiki page

A multi-purpose ARM-based small piggy-back PCB with Linux support, Ethernet, USB, sound, graphic LCD and lots of I/O pins.

The level conversion board project hosts a set of boards in VME form factor, with additional remote diagnostics/monitoring via I2C.

A three-channel TTL to NIM (Nuclear Instrumentation Module) level conversion board in VME form factor. More info at the Wiki page

A converter between USB/Ethernet and WorldFIP, allowing the bus arbitration and control of a WorldFIP fieldbus segment from a USB or Ethernet-equipped computer.

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

A High Pin Count FMC carrier in VXS format with two Virtex 5 FPGAs plus a DSP on board.

RHINO (Reconfigurable Hardware Interface for computiNg and radiO) is a compute platform consisting of a FPGA element with dedicated memory, high speed communication, and FMC-LPC (Vita 57.1) IO expansion slots, all controlled via an ARM Cortex A8 processor running the BORPH operating system.

For progress updates, follow us on twitter @rhinoplatform

Linux device driver and associated utilities for PCIe FMC carriers. Aka GnuRabbit.

A Virtex6-based optical link interface AMC equipped with SFP+ and FMC sockets

A transparent Wishbone bridge between two FPGAs using high-speed serial links. This project is on hold.* More info at the Wiki page

A card used in CERN's Linac 3 for the control of the electromagnetic field inside RF accelerating cavities.

An FMC to test the correct mounting of FMC connectors on FMC carrier boards.

OpenPicus is an Italian project made to fill the gap between Embedded Low Cost and Wireless. Picus modules are based on the well known Microchip PIC 24F 16bit processor connected to a Wireless Transceiver (WI-FI or BLUETOOTH). The OpenPicus Framework let you develop your Apps in easy way even without specific experience with Communication protocols. The IDE is also FREE and you can create, compile and download to the modules yoru Apps, no programming tools are needed.

An HPC FMC with 4 Digital to Analog Converter channels working at 250 MS/s with 16-bit resolution.

More information on the wiki page The design is currently used only for the CERN RF-group purposes

SPI Boards Package is a set of electronic boards developed at Soleil Synchrotron (France). These boards can be connected together in a daisy chain and they communicate with an embedded controller via an SPI Bus. They provide the following features:

- Platform allowing us to build specific solutions with simple and open tools.

- Modular architecture.

- Provide solutions for applications which require synchronization.

- Low level process implementation to achieve better performance. - Easy Control network connection

The main CPU board contains a microprocessor. It manages a task for communication with the supervision, an embedded process and SPI communication with the peripheral boards. We have a modular approach that means we can make various Peripheral board combinations between 16-bit DAC, 16-bit ADC, and a calculator board for motor encoder.

A Trigger/Timing Logic Unit designed for use with High Energy Physics beam-tests. Provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope. Connects to a FPGA carrier card via a FMC connector.

( N.B. Use the sub-project Git repositories, not the top level repository )