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Specific applications of open hardware modules are subprojects of this project. These subprojects contain specific firmware and/or software for existing hardware projects.

xTCAprojects shows the MTCA and uTCA boards that are developed in the Open Hardware Repository context. Keywords: MTCA.4, uTCA, AMC, MCH.

Software to support the FMC ADC 250M 16B 4CH mezzanine, including: configuration application and HDL firmware, with functionality for data acqusition. For use with FCS application. More info at the Wiki page

Software to support the FMC DIO 32CH TTL A mezzanine, including: configuration application and HDL firmware, with functionality for data acqusition. For use with FCS application. More info at the Wiki page

Software to support the FMC ADC 130M 16B 4CH mezzanine, including: configuration application and HDL firmware, with functionality for data acqusition. For use with FCS application. More info at the Wiki page

Software to support the FMC ADC 125M 14B 1CH DAC 600M 14B 1CH mezzanine, including: Linux device driver, HDL firmware, application for data acquisition (ADC) and generating signals (DAC). Included Octave application for card performance measurement (FFT). Uses FMC-bus. More info at the Wiki page

The project is a set of Kicad Symbols and Footprints that are used in a collection of smaller Kicad based sub projects. Each sub project will use the common library to ease and standardise design but will be a related implementation or documentation of a design. The topic for the Library and designs are Photo Multiplier Tube (PMT) based particle and optical detectors.

Whilst it is envisaged that each project will feature a PMT in some way. Some designs may not, but will be tangibly related in some useful way to particle detection and PMT's. For example a Divide by 10 HV PSU tester has no PMT but is used when working with the HV supply’s for PMT's. A High Voltage supply similarly has no PMT but is used with. A Geiger Muller Tube based detector may be used as a trigger source for PMT based particle detectors.

Each sub project is expected to be fully self contained (In it's own subdirectory within the same repository as PMTLib) with the exception of common Kicad Libraries and the inclusion of the PMTLib libraries and foot prints. A sub project may include a simulation of the design. Such simulations will be constructed using Open source Tools (ie QUCS or similar). PCB Layouts, Datasheets, PDF's and Photographs of finished designs may also be included. A sub project will contain at a minimum a Schematic and a README doc detailing attribution,licensing and any additional notes the designer wants to add.

Having mentioned the README doc the principle place for design related notes is on the Schematic that defines the sub-project.

The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.

Software for ROBIN-NP project.

Firmware for ROBIN-NP project.

Hardware designs for ROBIN-NP project.

GTS is a tool which takes a binary for a given microprocessor (initially an LM32) and gives information about worst-case execution time.

IPBus is a FPGA Core that controls a Wishbone bus via Ethernet. Currently the transport protocol is UDP/IP, although there are plans for an ATA over Ethernet (AoE) implementation. There are reference designs for the SP601 and SP605 Xilinx FPGA boards.

Details at http://ipbus.web.cern.ch/ipbus/

PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor.

Wherever possible, PHASE fetches design descriptions from the internet based on the detected JTAG IDCODEs, USB vendor IDs, or PnP BUS information. In the preceding example, each step of the chain would be automatically detected. The USB cable from the vendor+product codes, the FPGA from the JTAG IDCODE and the LM32 from the Arria2's sld hub. The user would now be presented with read/write access to the data and instruction buses for visual inspection or firmware loading. Furthermore, the user could launch gdb to halt and single-step the embedded LM32 CPU.

If a device is not yet described, the user may assemble a driver out of the reusable software components. For example, an Altera USB-Blaster driver is just a FTDI device chained with a byte packeter and a JTAG bit banger. Once the design has been graphically assembled, it is automatically scanned for attached JTAG devices and the USB cable design is shared online with any future users of the same cable.

Projects not directly identifiable with PCB or HDL core developments.