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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

Idrogen is an Arria10 FPGA board with FMC mezzanine.

PCB design is performed by IJCLab / CNRS-IN2P3. Firmware is developed by Observatoire Radioastronomique de Nançay (ORN) / Observatoire de Paris/ CNRS-INSU

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.

A board that has eyes

Active 32/64 channels 19" patch panel for FPGA boards, with robust 5V TTL I/Os, configurable through I²C and USB-C. More info at the Wiki page

A Precise Time Protocol (PTP, IEEE 1588) software stack whose single source code can be compiled for many architectures (POSIX systems, WR switch, WR node, ...) and which is easily extensible.

A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page

SAMD21-based monitoring module for DI/OT power supply and fan tray.

The open-source HEV ventilator implements the modes PC-A/C, PC-A/C-PRVC, PC-PSV and CPAP More info at the Wiki page

A UV-mask meant for people with a highly sensitive skin. It features 100% protection from UV and has an integrated fan. The design is fully open. More info at the Wiki page

The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page

DIOT reliability studies files and reports. More info at the Wiki page

A project devoted to developing and discussing the CERN Open Hardware Licence. More info at the Wiki page

Hardware and software (libraries and GUI) to implement the SFF-8472 standard “Diagnostic Monitoring Interface for Optical Transceivers”. The hardware implements four SFP+s that can be exercised in parallel. To access the I2C interfaces a USB to I2C chip is used. More info at the Wiki page

High performance pulse and frequency distribution amplifier for time and frequency metrology. The pulse distribution board is an 1:8-channel (1 Hz and up) logic-level distribution amplifier, while the frequency distribution board is an 1:8-channel sine-wave (1-30 MHz) distribution amplifier. Two 1:8 boards fit side-by-sides in a 1U 19" rack enclosure, with either BNC or SMA connectors.

For more information, see the wiki

Hardware design of Conv TTL Blocking. Includes schematics, PCB layout and manufacturing files. More info at the Wiki page

This library provides a generic API for ADC devices, so that applications can use this API to access any of the supported ADC boards. Currently the library supports the following boards:

fmc-adc-100m14b14cha

For testing and debugging purpose it supports also a couple of virtual boards that you can use to start the development of your application.

More info at the Wiki page

Gateware (HDL design) for FMC ADC 400k 18b 4cha iso on SPEC and SVEC carriers.

LIST is a trigger distribution system based on White Rabbit. It can receive a trigger from a “cloud” of devices and distribute it to all relevant devices to for example freeze their acquisition buffers. The latency between reception and transmission of a trigger is done with a low and notably fixed latency, with an accuracy of better than 1 ns. The hardware of the LIST nodes is based on the SVEC FMC carrier equipped with a FMC TDC mezzanine and a Fine Delay mezzanine. More info at the Wiki page