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ELMB2 is an analog/digital I/O module with CANbus interface. They are used in various CERN installations in control and monitoring of equipment. The ELMB2 is radiation qualified. More info at the Wiki page
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We have designed an FPGA Mezzanine card (standard FMC/Vita 57) for high-channel-count electrophysiology, with 128 channels (potentially up to 512), based upon Intan Tech's RHA2132 (2 uV rms input-referred noise), sampled at 25kHz 18bit by AD7982. We are basing our design on the reference design provided by Reid Harrison of Intan Tech for their 16-channel evaluation board. The expected cost of the device should be under 5000$.
In order to have an integrated solution we intend to have as default carrier the Opal Kelly Shuttle LX1, an inexpensive USB FMC carrier with an excellent USB controller. The integrated solution will be completed with software on the PC side to grab to disk continuously and/or display in some fashion all 128 channels.
Our status: We have an alpha card. It has passed most tests---we can grab from any channel at 1MS/s. We have an alpha microcode: it grabs from any channel and stores on the PC.
Our current team: Marcelo Magnasco (Rockefeller University, New York), design. Andres Cicuttin (ICTP, Trieste), schematics + fpga Maria Liz Crespo (ICTP, Trieste), fpga Sanjee Abeytunge (MSKCC, New York) layout Nicholas Joseph (RU) Macintosh drivers
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The OPT ADC 10k 32b 1cha is a single channel 10kSPS 32 bit ADC card in the format defined by the CERN TE-EPC group for use with the Function Generator Controller (FGC 3.2) . It is also known under the name HPM7177.
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Projects / SIS1160 PCI-L IO add on
CERN Open Hardware Licence Version 2 - Weakly ReciprocalA front-end PCI board with LEMO connectors to interface with the GPIO interconnect pins of the SIS1160 FMC carrier. More info at the Wiki page
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A 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). SPEC carrier based with a larger FPGA. Commercially available. More info at the Wiki page
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A UV-mask meant for people with a highly sensitive skin. It features 100% protection from UV and has an integrated fan. The design is fully open. More info at the Wiki page
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Projects / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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DI/OT Igloo2-based System Board for radiation-exposed DI/OT applications. More info at the Wiki page
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DIOT 3U crate mechanics and backplane compliant with CompactPCI-Serial standard.
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Idrogen is an Arria10 FPGA board with FMC mezzanine.
PCB design is performed by IJCLab / CNRS-IN2P3. Firmware is developed by Observatoire Radioastronomique de Nançay (ORN) / Observatoire de Paris/ CNRS-INSU
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Distributed I/O Tier - these are electronics modules installed close to a particle accelerator in radiation-exposed or radiation-free areas controlled by the master in the Front-end tier over the fieldbus. These are usually FPGA-based boards sampling digital and analog inputs, driving outputs and performing various safety critical operations. More info at the Wiki page
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DI/OT Kintex Ultrascale-based Peripheral Board with HPC FMC and SODIMM DDR4 slot. More info at the Wiki page
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White Rabbit Switch WRS-3/18 (hardware version 3.4) with the low-jitter daughterboard integrated. More info at the Wiki page
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The aim of the board is to improve the performance of the WR Switch using an external PLL and a new VCTCXO. More info at the Wiki page
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SAMD21-based monitoring module for DI/OT power supply and fan tray.
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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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Projects / PPSi
GNU Lesser General Public License v2.1 onlyA Precise Time Protocol (PTP, IEEE 1588) software stack whose single source code can be compiled for many architectures (POSIX systems, WR switch, WR node, ...) and which is easily extensible.
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This project defines data structures, to be embedded in the FPGA memory address space, to enumerate the devices that have been synthetized in the current design. The same structure is also used as a simple flash file system. AKA Self-Describing Bus (SDB) Specification for Logic Cores. The layout is simple enough to be parsed both by the host and by the internal soft-core, if any.
The documentation is public, and related code is GNU GPL licensed.
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A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available. More info at the Wiki page
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An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page
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