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A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page

A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.

Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Hardware.

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Testing.

The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA

Compact Universal Timing Endpoint Based on White Rabbit with Xilinx Artix7. Follow-up of the CUTE-WR-DP. More info at the Wiki page

AFCKU is dual FMC carrier in AMC format based on Kintex Ultrascale SoC devices. It supports White Rabbit and RTM modules. More info at the Wiki page.

A low cost potentiostat circuit to perform electrochemistry experiments. The system may be driven by a Teensy card from PJRC (Arduino IDE) or by power supplies, More info at the Wiki page

FMC LPC card with two High Voltage (HV) outputs and one Low Voltage (5-10V) output. Has mV voltage sensing and mA current sensing capabilities. More info at the Wiki page

The Analogue GIRAPH is an active 19" patch panel that provides 32 single ended or 16 diff. analogue inputs and 8 channels single-ended analogue output. More info at the Wiki page

Collection of WRTD reference designs provided by (and used at) CERN

Idrogen is an Arria10 FPGA board with FMC mezzanine.

PCB design is performed by IJCLab / CNRS-IN2P3. Firmware is developed by Observatoire Radioastronomique de Nançay (ORN) / Observatoire de Paris/ CNRS-INSU

A Trigger/Timing Logic Unit to synchronize devices at beam test A successor to the AIDA(2020) TLU (https://ohwr.org/project/fmc-mtlu) This is an "umbrella" project with documentation, pointing to the projects with the hardware and firm(gate)ware

Hardware design of the PandABox. Includes schematics, PCB layout and manufacturing files.

Neo51 is an open source hardware based on 89V51 microcontroller. It has a dual mode feature selectable via DIP switch supporting arduino hardware compatible ports and the legacy 8051 ports.

Host-side software support for the TDC FMC on the SPEC and SVEC FMC carriers.

More info at the Wiki page

HW project: https://www.ohwr.org/project/fmc-tdc/wiki

ADC testing procedures and software. More info at the Wiki page

Utility project for the CERN BE-CO-HT Continuous Integration (CI) infrastructure.