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Projects / AIDA-2020 TLU - Hardware
CERN Open Hardware Licence v1.2Updated -
A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor.
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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
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Introductory SoC course with reference designs based on the Xilinx Vitis Unified Software Development Platform and targeted to the Xilinx Zynq UltraScale+ MPSoC. More info at the Wiki page
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Projects / 3DMASK - 3D printed mask
CERN Open Hardware Licence Version 2 - PermissiveThis open-source 3DMASK offers a FFP2-level protection with the right filter material. It can be produced by anybody in possession of a 3D printer. More info at the Wiki page.
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The Face Shield, made only for COVID-19 protection, can be worn directly or can be put on safety helmets. The FaceShield is developed under the CERN against COVID-19 program. More info at the Wiki page
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VentilatorPAL is a high-quality and low-cost, open source ventilator. More info at the Wiki page
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OpenBreath / Open Breath PEP Whistle
CERN Open Hardware Licence Version 2 - Strongly ReciprocalUpdated -
Intel Arria V based VME64x carrier for one high pin count FMC with six SFP connectors, DDR3 memory and clocking resources to support White Rabbit. For more details please refer to the wiki pages.
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pcie-fmc-soc-vdas is a PCIe carrier for a high pin count FPGA Mezzanine Card (VITA 57). The main component is a SOC chip used in cellular base stations that can do advanced processing. More info at the Wiki page
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A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.
The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.
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The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
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Projects / Euro ADC 65M 14b 40cha hw PUMA-hw
CERN Open Hardware Licence v1.2Updated -
PUMA (Plataforma Utilizada para el Muestreo de Arapuca) is a multi-channel digitizer designed to instrument the photon detection system for the DUNE Photon Detection System. However, it may be useful for other applications that require 40 - 64 channels of 14-bit digitzier sampling at 10MSample/s - 65MSample/s. PUMA is based on the digitizer designed for the SoLiD short baseline reactor neutrino detector. It is designed to be connected to external signal conditioning modules, which are controlled by I2C. More info at the Wiki page
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The DAPHNE front end board is a piece of hardware that digitizes the output signal from one of the systems of the far detector in the DUNE experiment. For more information, see the wiki
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