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VHDL core for absolute position encoders (SSI, BISS, ENDAT).

More info at the Wiki page

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

Firmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )

A low cost, low complexity FMC carrier based on Xilinx Artix-7

The AsyncArt Project is comprised by a set of Open-Source HDL libraries and examples targeted to the efficient implementation of Globally Asynchronous, Locally Synchronous (GALS) design architectures over Commercial-Off-The-Shelf FPGA devices.

BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page

Gateware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

Common gateware for the different level conversion circuits.

Gateware (VHDL) for the level conversion board Conv TTL Blocking in VME64x form factor between TTL and blocking levels. More info at the Wiki page

Production and functional tests for Conv TTL Blocking. More info at the Wiki page

Gateware (HDL design) for Conv TTL RS485

Production and functional tests for Conv TTL RS485

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.

FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). More info at the Wiki page