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The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.
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FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
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The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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Pascal Bos / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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Brian Koropoff / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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Legacy-VME64x core implements a legacy VME (VMEbus IEEE-1014) and VME64x (based on the vme64x-core) slave.
The core offers for SoC interconnection:
Master WB interconnection and Slave WB for MSI IRQ.The core also provides a universal layer abstraction for common hardware components in VME design (e.g VME buffers). It allows for geographical and hardware switch addressing. More info at the Wiki page
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A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).
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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
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Projects / AIDA-2020 TLU - Software
GNU Affero General Public License v3.0Updated -
Mathieu Saccani / VME64x core - msaccani
GNU Lesser General Public License v2.1 onlyA VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
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Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page
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FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). More info at the Wiki page
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Projects / powerlink
BSD 3-Clause "New" or "Revised" LicensePowerlink Industrial Ethernet stack. It runs on top of the Hydra rad-tol SoC project. More info at the Wiki page
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Hydra is a RISC-V based radiation-tolerant SoC designed to operate up to 500 Gy TID. See the wiki for more details.
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Projects / VHDL macro libraries for Microsemi ProASIC3
GNU Affero General Public License v3.0This is a collection of simple macro implementations for Microsemi's ProASIC3 FPGAs to allow simulating post-synthesis designs using GHDL.
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