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BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page
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Projects / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).
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This project covers the hardware development of version 4 of the White Rabbit switch (WRS-v4). More info at the Wiki page
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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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A project to host all software and hardware developments related to testing the White Rabbit switch.
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Distribution of clock signals over a White Rabbit network. It uses an PLL with a numerically controlled (DDS) oscillator to extract the characteristics of a signal that in turn are distributed over a White Rabbit network to receiving nodes with a DAC that regenerate exactly the same signal in phase. More info at the Wiki page
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Project containing information about how to calibrate White Rabbit gear. See also https://www.ohwr.org/project/white-rabbit/wikis/Calibration More info at the Wiki page
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A VME card that is used to recover RF, bunch and revolution clocks over a white rabbit network.
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Projects / Wishbone slave generator
Affero General Public License v1.0wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:
- Automatically allocated memory layout
- VHDL/Verilog code for the slave module
- C header files for driver development - Nice HTML documentation
Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2
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VME board with 36 ADC channels with a sampling rate of 250 kS/s and 16 bits resolution. More info at the Wiki page
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VHDL coding style document to be used at ohwr.org The project contains also a tool to automatically check the coding style. More info at the Wiki page
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The TimEX3 is a multipurpose compact PCI board designed to perform simple to medium complex logical functions. It is mainly used for the synchronization system of SOLEIL (signal duplication, top-up gating, etc.). This board is based on a Spartan-6 FPGA and PLX PCI9030 interface. It is designed with KiCad software, and released under CERN OHL License.
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A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page
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A simple 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Linux and Labview drivers available for some mezzanine cards. More info at the Wiki page
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Detailed documentation on how to get ready to work with the Simple PCI Express Carrier, including hardware deployment instructions, full required toolchain setup and and a collection of step-by-step demonstrative tutorials.
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A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page
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