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  • Projects / FMC ADC 1G 8b 2cha

    The FmcAdc1G8b2cha is a 2 channel 1GSPS 8 bit ADC card in FMC (FPGA Mezzanine Card, VITA 57.1) format using a Low Pin-Count (LPC) connector.

    Currently in Planning phase.

    More info at the Wiki Page

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  • Projects / FMC DIO 5ch TTL a

    FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page

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  • Projects / FMC TDC 1ns 5cha

    An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page

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  • Projects / fmc dac 600m 12b 1cha dds - Testing

    Production and functional tests for fmc-dac-600m-12b-1cha-dds

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  • Projects / Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP

    The CUTE-WR-DP is the enhanced version of CUTE-WR with dual WR ports. You can use it as the normal WR node with one SFP port. CUTE-WR-DP can work in chain to support cascade topology. In future, CUTE-WR-DP could support dualport redundancy function for high reliable application. More info at the Wiki page

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  • Projects / White Rabbit low jitter

    Project exploring the current limits of White Rabbit timing distribution and how to obtain the best possible jitter and Allan Deviation performance

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  • Projects / FMC DIO 10I 8O

    FmcDIO10i8o is an I/O card in FMC form-factor. Its 10 inputs use fast differential comparators (propagation delay < 1 ns) with individual 8-bit DACs of minimum 1 MSPS output settling. The 8 outputs are TTL level. More info at the Wiki page

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  • Projects / FPGA and ARM SoC FMC Carrier FASEC

    A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page

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  • Projects / WRAP

    WRAP, White RAbbit Pluggable, is a plug-in board providing easy-to-use WR functionality. Among others it provides direct 10MHz and PPS (pulse per second) outputs.

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  • Projects / EMC2-DP

    PC/104 OneBank Carrier for SoC Modules. The EMC2-DP is a PCIe/104 OneBank Carrier for a Trenz compatible SoC Module and has expansion for a VITA57.1 FMC LPC I/O board and also has I/O pins, using a 100-way Samtec RazorBeam connectors system. Board developed with EU funding on the Artemis EMC2 project. More info at the Wiki page

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  • Projects / WRS Fan-less hardware

    Fanless version of the White Rabbit Switch WRS-3/18 (hardware version 3.4) with the low-jitter daughterboard integrated. More info at the Wiki page

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  • Projects / AIDA-2020 TLU - Gateware

    FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

    Uses "IPBus Build" ( ipbb )

    Build instructions at Instructions here

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  • Projects / Companies

    Companies using the Open Hardware Repository

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  • Projects / SPEC7

    A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page

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  • Projects / Level conversion circuits

    The level conversion board project hosts a set of boards in VME form factor, with additional remote diagnostics/monitoring via I2C.

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  • Projects / HiCCE-FMC-128

    We have designed an FPGA Mezzanine card (standard FMC/Vita 57) for high-channel-count electrophysiology, with 128 channels (potentially up to 512), based upon Intan Tech's RHA2132 (2 uV rms input-referred noise), sampled at 25kHz 18bit by AD7982. We are basing our design on the reference design provided by Reid Harrison of Intan Tech for their 16-channel evaluation board. The expected cost of the device should be under 5000$.

    In order to have an integrated solution we intend to have as default carrier the Opal Kelly Shuttle LX1, an inexpensive USB FMC carrier with an excellent USB controller. The integrated solution will be completed with software on the PC side to grab to disk continuously and/or display in some fashion all 128 channels.

    Our status: We have an alpha card. It has passed most tests---we can grab from any channel at 1MS/s. We have an alpha microcode: it grabs from any channel and stores on the PC.

    Our current team: Marcelo Magnasco (Rockefeller University, New York), design. Andres Cicuttin (ICTP, Trieste), schematics + fpga Maria Liz Crespo (ICTP, Trieste), fpga Sanjee Abeytunge (MSKCC, New York) layout Nicholas Joseph (RU) Macintosh drivers

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