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Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.

4-channel 16-bit 250 MS/s (700 MHz analog input bandwidth) ADC (ISLA216P25) FMC module.

Collection of WRTD reference designs provided by (and used at) CERN

The image processing library offers multiple cores for on-chip vision-feature extraction. HDL modules are provided in different languages such as Handel-C or VHDL and applicable to various embedded and reconfigurable devices. They can be of interest for applications such as particle tracking, analysis of fluid dynamics, artificial vision for robotics, or object recognition.

The spec-box-1n allows to use a SPEC FMC carrier in stand-alone mode, not plugged inside a PC. An external 12 volt supply should be used to power the box. There is no forced ventilation in the box. More info at the Wiki page

pcie-fmc-soc-vdas is a PCIe carrier for a high pin count FPGA Mezzanine Card (VITA 57). The main component is a SOC chip used in cellular base stations that can do advanced processing. More info at the Wiki page

The B-Train integrator is a 2 differential channel 2MSPS 18 bit ADC card in FMC (FPGA Mezzanine Card) format. It uses an LPC VITA57 connector. The gain can be set by hardware (default = 1). A gain & offset self-calibrating function is also implemented. This function uses a 1ppm 20-Bit DAC (AD5791) as a reference and can be programmed as a differential voltage source. The card also includes 8 input/output LVDS pairs and a 10-bit port digital IO where each single-bit port can be configured individually as input or output. The I/Os that are on micro-HDMI connectors are TTL or LVDS compatible.

Firmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )

A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.

The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.

FMC DAC 10M 16b 4cha: 16-bit 10Ms/s DAC card in FMC form-factor. Four channels with an output range of +/-10V. Three trigger inputs (start, pause and stop), common to the four outputs.

Cancelled project.

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

FMC mezzanine board that connects to an Xilinx Virtex-6 FPGA ML605 evaluation board that allows transmitting through 12-channel MPO optical devices a set of 72 links aimed for low-speed (general I/O from the Virtex 6, up to 480 Mbps) and 8 links for high-speed multigigabit transmitters of the Virtex 6 (up to 1600 Mbps). This boards is used for testing other devices. More info at the Wiki page

Project containing information about how to calibrate White Rabbit gear. See also https://www.ohwr.org/project/white-rabbit/wikis/Calibration More info at the Wiki page

The FmcAdc250M12b2cha is a 2 channel 250MSPS 12 bit ADC card in FMC (FPGA Mezzanine Card) format using an LPC connector. The gain can be set by software in three steps: /-50mV,/-0.5V, /-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of/- 5V that is independent on the chosen gain range.

Yocto Project / OpenEmbedded meta layer supporting the use of the Simple PCIe Carrier (SPEC) in x86 and x86-64 embedded Linux hosts. It features:

SPEC software (kernel, userspace, library, gateware) White Rabbit Interface Card support. White Rabbit Starting Kit demos. Getting started with the SPEC demos (python, gateware) Ready to go minimal and sato image recipes.

The Analogue GIRAPH is an active 19" patch panel that provides 32 single ended or 16 diff. analogue inputs and 8 channels single-ended analogue output.

The PFC is a 4-lane PCIe carrier for a single VITA 57 (FMC) mezzanine. It has many memory and clocking resources and supports the White Rabbit timing and control network. For more details please refer to the Wiki pages. *Warning. This project is on hold. Refer to the SPEC*

Software support for the SPEC board, including kernel and user-space Linux code. The package also include the fmc-bus driver, which is expected to be used by other carriers as well.

BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page