Explore projects
-
A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
Updated -
A VHDL core for a PCI slave. The other side behaves like a Wishbone master.
More info at the Wiki pageUpdated -
The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
Updated -
Couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP. More info at the Wiki page
Updated -
A low cost, low complexity FMC carrier based on Xilinx Artix-7
Updated -
DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.
Updated -
This project contains all the HDL gateware necessary for the FPGA of the WR switch.
Updated -
-
Production and functional tests for PXIe controller COM Express based. More info at the Wiki page
Updated -
This project contains all the HDL gateware necessary for the FPGA of the WR switch.
Updated -
Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.
Updated -
Gateware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.
Updated -
Distribution of clock signals over a White Rabbit network. It uses an PLL with a numerically controlled (DDS) oscillator to extract the characteristics of a signal that in turn are distributed over a White Rabbit network to receiving nodes with a DAC that regenerate exactly the same signal in phase. More info at the Wiki page
Updated