Explore projects
-
A meta project used to discuss and present information about Open Hardware and related subjects. More info at the Wiki page More info about the CERN Open Hardware licence More info about the OHR.org site support
Updated -
-
The FmcAdc1G8b2cha is a 2 channel 1GSPS 8 bit ADC card in FMC (FPGA Mezzanine Card, VITA 57.1) format using a Low Pin-Count (LPC) connector.
Updated -
FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page
Updated -
Projects / PPSi
GNU Lesser General Public License v2.1 onlyA Precise Time Protocol (PTP, IEEE 1588) software stack whose single source code can be compiled for many architectures (POSIX systems, WR switch, WR node, ...) and which is easily extensible.
Updated -
Production and functional tests for fmc-dac-600m-12b-1cha-dds
Updated -
The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
Updated -
Projects / Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP
MIT LicenseThe CUTE-WR-DP is the enhanced version of CUTE-WR with dual WR ports. You can use it as the normal WR node with one SFP port. CUTE-WR-DP can work in chain to support cascade topology. In future, CUTE-WR-DP could support dualport redundancy function for high reliable application. More info at the Wiki page
Updated -
A White Rabbit Timing Receiver in AMC (Advanced Mezzanine Card, AdvancedMC) format. More info at the Wiki page
Updated -
Project exploring the current limits of White Rabbit timing distribution and how to obtain the best possible jitter and Allan Deviation performance
Updated -
FmcDIO10i8o is an I/O card in FMC form-factor. Its 10 inputs use fast differential comparators (propagation delay < 1 ns) with individual 8-bit DACs of minimum 1 MSPS output settling. The 8 outputs are TTL level. More info at the Wiki page
Updated -
A White Rabbit Timing Receiver in PMC (PCI Mezzanine Card) format. More info at the Wiki page
Updated -
A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page
Updated -
WRAP, White RAbbit Pluggable, is a plug-in board providing easy-to-use WR functionality. Among others it provides direct 10MHz and PPS (pulse per second) outputs.
Updated -
PC/104 OneBank Carrier for SoC Modules. The EMC2-DP is a PCIe/104 OneBank Carrier for a Trenz compatible SoC Module and has expansion for a VITA57.1 FMC LPC I/O board and also has I/O pins, using a 100-way Samtec RazorBeam connectors system. Board developed with EU funding on the Artemis EMC2 project. More info at the Wiki page
Updated -
Projects / AIDA-2020 TLU - Software
GNU Affero General Public License v3.0Updated -
This project covers the hardware development of version 4 of the White Rabbit switch (WRS-v4). More info at the Wiki page
Updated -
A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page
Updated -
Projects / AIDA-2020 TLU - Gateware
GNU General Public License v3.0 or laterFPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
Updated -
Projects / AIDA-2020 TLU - Hardware
CERN Open Hardware Licence v1.2Updated