Explore projects
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A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page
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Production and functional tests for Conv TTL Blocking. More info at the Wiki page
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Projects / Wishbone slave generator
Affero General Public License v1.0wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:
- Automatically allocated memory layout
- VHDL/Verilog code for the slave module
- C header files for driver development - Nice HTML documentation
Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2
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David Cussans / AIDAInnova_TLU-gw
GNU General Public License v3.0 or laterFirmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )
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The nanoFIP test board is used to test the functionality of the nanoFIP design. Apart from the nanoFIP chip, the FielDrive and the FieldTR it houses another Actel FPGA that can access nanoFIP in stand-alone or in memory mode. This FPGA can also communicate through a RS232 port with a windows PC running the NFTC software. The components on the board are placed in such a way that with a focused beam, radiation tests can be performed to the nanoFIP, FielDrive and FieldTR, leaving the rest if the components in a radiation-safe zone. The card has been designed by the company HLP.
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Distribution of clock signals over a White Rabbit network. It uses an PLL with a numerically controlled (DDS) oscillator to extract the characteristics of a signal that in turn are distributed over a White Rabbit network to receiving nodes with a DAC that regenerate exactly the same signal in phase. More info at the Wiki page
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The TimIQ system is an IQ modulator allowing to phase shift a radio frequency clock with a resolution of 40 fs and an accuracy of 8 ps. Hardware.
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A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.
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VHDL core for absolute position encoders (SSI, BISS, ENDAT).
More info at the Wiki pageUpdated -
BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page
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Brian Koropoff / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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A VHDL core for a PCI slave. The other side behaves like a Wishbone master.
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Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page
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Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.
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Hydra is a RISC-V based radiation-tolerant SoC designed to operate up to 500 Gy TID. See the wiki for more details.
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TiCkS is a flexible White Rabbit based time-stamping board. It is based on the SPEC board developed for the CTA collaboration. It provides an interface to a CTA camera (Inputs: Read-out Trigger signals, Busy Trigger), (Outputs: PPS signal , 10MHz clock, External trigger signal).
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Project containing information about how to calibrate White Rabbit gear. See also https://www.ohwr.org/project/white-rabbit/wikis/Calibration More info at the Wiki page
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