Modifications to clocking:

Edited logic_clocks.vhd to generate strobes for 320MHz and 160MHz clock domains from 40MHz clock supplied by PLL ( not shift register ). Should be more robust.

Data signals ( Trigger , Sync/T0 ) still delayed by ~ 3ns with respect to Si5345 clock on DUT cables ( see https://webapps-pp.bris.ac.uk/elog/AIDA/105 )

Fixes to 1e000020

Added registers to give reset and trigger lines same relationship with clock in AIDA+trigger-num mode 

Builds (at least once... ) to give bitstream who's behaviour matches simulation

Was seeing behaviour in hardware not seen in simulation. Put in reset circuitry to AIDA DUT interface. Added one extra register for clk4x (160MHz) outputs.

Added ability to clock out trigger number in AIDA (synchronous) handshake mode

Tidied up timing constraints. May help with problems seen at DESY with 1e000014