Modifications to clocking: Edited logic_clocks.vhd to generate strobes for 320MHz and 160MHz clock domains from 40MHz clock supplied by PLL ( not shift register ). Should be more robust. Data signals ( Trigger , Sync/T0 ) still delayed by ~ 3ns with respect to Si5345 clock on DUT cables ( see https://webapps-pp.bris.ac.uk/elog/AIDA/105 )