set xlib_vhdl $::env(ISE_VHDL_MTI)
set xlib_vlog $::env(ISE_VLOG_MTI)

project new ./ fmc_tlu_sim
vmap unisim $xlib_vhdl/unisim
vmap unimacro $xlib_vhdl/unimacro
vmap secureip $xlib_vlog/secureip
vmap xilinxcorelib $xlib_vhdl/xilinxcorelib

project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/example_designs/hdl/clock_div.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipcore_dir/mac_fifo_axi4.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/transactor.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/stretcher.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
project addfile $::env(FW_WORKSPACE)/workspace/external/opencores_i2c/i2c_master_registers.vhd
project addfile $::env(FW_WORKSPACE)/workspace/external/opencores_i2c/i2c_master_byte_ctrl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/external/opencores_i2c/i2c_master_bit_ctrl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/syncreg_w.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/syncreg_r.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipcore_dir/tlu_event_fifo.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipcore_dir/internalTriggerGenerator.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipcore_dir/FIFO.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/external/opencores_i2c/i2c_master_top.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd

project calculateorder
project close
quit

