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wr2rf-vme
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RF signal, distributed to trigger unit flip flops looks awful
#74
· opened
Jan 22, 2021
by
John Gill
Layout V2
critical
hw
CLOSED
2
updated
Feb 05, 2021
WRC eeprom are too small
#72
· opened
Dec 14, 2020
by
Tristan Gingold
Layout V2
hw
CLOSED
1
updated
Feb 05, 2021
OCXO sense goes to FPGA digital input
#71
· opened
Dec 14, 2020
by
Dimitris Lampridis
Layout V2
hw
important
CLOSED
1
updated
Feb 05, 2021
SFP LEDs are on when FPGA is not programmed
#70
· opened
Dec 14, 2020
by
Dimitris Lampridis
Layout V2
hw
minor
CLOSED
2
updated
Feb 05, 2021
Unconnected 5V power rail
#69
· opened
Dec 14, 2020
by
John Gill
Layout V2
critical
hw
CLOSED
1
updated
Feb 05, 2021
Cross check PCB labelling with front panel for the SFP indexing
#68
· opened
Dec 14, 2020
by
John Gill
Layout V2
cosmetics
for-DEM
hdl
hw
CLOSED
2
updated
Feb 15, 2021
Should RF trigger driver be powered from P3V3A?
#45
· opened
Jun 30, 2020
by
Dimitris Lampridis
Schematic done
hw
question
CLOSED
2
updated
Jul 07, 2020
Replace ADCLK925 with LTC6957-2
#44
· opened
Jun 29, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
18
updated
Jul 08, 2020
Missing correct symbols in rf_main sheet
#43
· opened
Jun 12, 2020
by
Mattia Rizzi
Schematic done
critical
hw
CLOSED
1
updated
Jun 12, 2020
Feature: digital potentiometer for pulse_shaper
#42
· opened
May 28, 2020
by
Mattia Rizzi
cosmetics
hw
CLOSED
1
updated
Jun 09, 2020
10Mhz out: from pll or from fpga ?
#41
· opened
May 20, 2020
by
Tristan Gingold
hdl
hw
question
CLOSED
4
updated
Jun 16, 2020
Use separate FPGA pins for the two WR EEPROMs
#40
· opened
May 19, 2020
by
Dimitris Lampridis
Schematic done
hdl
hw
important
xdc update
CLOSED
3
updated
Jun 29, 2020
delay line for TU
#39
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
CLOSED
3
updated
Jun 25, 2020
BOM de de-optimization
#38
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
CLOSED
1
updated
Jun 06, 2020
Power sequencing and consumption
#37
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
7
updated
Jun 29, 2020
Consider serial termination on the LEN pin of the 100EP195 delay line
#36
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
minor
CLOSED
1
updated
Jun 09, 2020
Check DDS IOUPDATE signal FPGA connection
#35
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
question
CLOSED
1
updated
Jun 09, 2020
Dielectric of ceramic capacitors in the RF path
#34
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
important
CLOSED
3
updated
Jun 10, 2020
Main RF generation
#33
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
question
CLOSED
3
updated
Jun 09, 2020
DAC clock - AC coupling
#32
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
critical
hw
CLOSED
9
updated
Jun 30, 2020
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