Check DDS IOUPDATE signal FPGA connection
I'm not 100% sure having two single-ended pins (possibly driven from different clock domains) belonging to the same differential pair (e.g. pins AC13, AD13) will P&R correctly. Maybe worth checking.
I'm not 100% sure having two single-ended pins (possibly driven from different clock domains) belonging to the same differential pair (e.g. pins AC13, AD13) will P&R correctly. Maybe worth checking.