hacked spll_proxy

4499a1cb · Maciej Lipinski · b4786303 · 4499a1cb · 4499a1cb · 4499a1cb
Commit 4499a1cb authored Sep 14, 2021 by Maciej Lipinski
4 changed files
--- a/FCWR_tests/sw/tools/spll_proxy/Makefile
+++ b/FCWR_tests/sw/tools/spll_proxy/Makefile
+CROSS_COMPILE   =/home/mlipinsk/Developments/projects/2021-03-ZCU102_EVB/wr-switch-hw-v4-v3/FCWR_tests/sw/output/buildroot-2017.02/output/host/usr/bin/aarch64-buildroot-linux-gnu-
+WRS_SW_DIR	=../wr-switch-sw/
+ZCU_SW_DIR	=../wr-switch-hw-v4-v3/FCWR_tests/sw/
+
+CC              = $(CROSS_COMPILE)gcc
+CFLAGS          = \
+		-Wstrict-prototypes \
+		-I$(WRS_SW_DIR)userspace/include/ \
+		-I.
+#
+#		-I$(WRS_SW_DIR)userspace/libwr/include/ \
+#		-I$(ZCU_SW_DIR)output/buildroot-2017.02/output/build/uboot-xilinx-v2018.3/arch/arm/mach-at91/include \
+
+
+spll_dbg_proxy: spll_dbg_proxy.c
+	$(CC) -o spll_dbg_proxy spll_dbg_proxy.c $(CFLAGS)
+	
+clean:
+	rm -f *.o *~ spll_dbg_proxy
\ No newline at end of file
--- a/FCWR_tests/sw/tools/spll_proxy/fpga_io.h
+++ b/FCWR_tests/sw/tools/spll_proxy/fpga_io.h
+#ifndef __FPGA_IO_H
+#define __FPGA_IO_H
+
+#include <stdint.h>
+
+/* Base addresses of all FPGA peripherals used in libwr */
+
+/* PPS Generator */
+#define FPGA_BASE_PPS_GEN      0x10500
+
+/* Aux Clk Generator */
+#define FPGA_BASE_GEN_10MHZ    0x10600
+
+/* Routing Table */
+#define FPGA_BASE_RTU          0x60000
+
+/* Simple PWM module */
+#define FPGA_BASE_SPWM         0x55000
+
+/* HW Info Unit */
+#define FPGA_BASE_HWIU         0x59000
+
+/* Topology Resolution Unit */
+#define FPGA_BASE_TRU          0x56000
+
+/* Time-Aware Traffic Shaper Unit */
+#define FPGA_BASE_TATSU        0x57000
+
+/* per-port Statistics */
+#define FPGA_BASE_PSTATS       0x58000
+
+/* HardWare Debugging Unit */
+#define FPGA_BASE_HWDU         0x59000
+
+/* Watchdog Module */
+#define FPGA_BASE_WDOG         0x5A000
+
+/* Endpoint  */
+#define FPGA_BASE_EP0          0x30000
+
+/* NIC */
+#define FPGA_BASE_NIC          0x20000
+
+extern volatile uint8_t        *_fpga_base_virt; /* libwr/fpga_io.c */
+
+#define FPGA_BASE_ADDR          _fpga_base_virt
+
+
+#define _fpga_writel(reg, val) \
+	(*(volatile uint32_t *)(FPGA_BASE_ADDR + (reg)) = (val))
+#define _fpga_readl(reg) \
+	(*(volatile uint32_t *)(FPGA_BASE_ADDR + (reg)))
+
+#endif
--- a/FCWR_tests/sw/tools/spll_proxy/softpll-regs.h
+++ b/FCWR_tests/sw/tools/spll_proxy/softpll-regs.h
--- a/FCWR_tests/sw/tools/spll_proxy/spll_dbg_proxy
+++ b/FCWR_tests/sw/tools/spll_proxy/spll_dbg_proxy