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White Rabbit Switch - Hardware V4
Commits
b4786303
Commit
b4786303
authored
Aug 25, 2021
by
Jorge Machado
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Allow access from PS to the wb memory space
parent
997e32e4
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6 changed files
with
1333 additions
and
371 deletions
+1333
-371
fmc_support_bd.tcl
FCWR_tests/fmc_support_gw/syn/fmc_support_bd.tcl
+9
-3
component.xml
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/component.xml
+652
-364
axi4_pkg.vhd
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/src/axi4_pkg.vhd
+292
-0
wb_axi4lite_bridge.vhd
.../fmc_support_gw/vivado_ip/wrpc/src/wb_axi4lite_bridge.vhd
+125
-0
xwb_axi4lite_bridge.vhd
...fmc_support_gw/vivado_ip/wrpc/src/xwb_axi4lite_bridge.vhd
+185
-0
zcu102.vhd
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/src/zcu102.vhd
+70
-4
No files found.
FCWR_tests/fmc_support_gw/syn/fmc_support_bd.tcl
View file @
b4786303
...
...
@@ -659,7 +659,7 @@ proc create_root_design { parentCell } {
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0
]
set_property -dict
[
list
\
CONFIG.NUM_MI
{
5
}
\
CONFIG.NUM_MI
{
6
}
\
]
$axi
_interconnect_0
# Create instance: clk_wiz_0, and set properties
...
...
@@ -700,6 +700,9 @@ proc create_root_design { parentCell } {
# Create instance: rst_ps8, and set properties
set rst_ps8
[
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8
]
# Create instance: rst_ps9, and set properties
set rst_ps9
[
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps9
]
# Create instance: sfp_axi_gpio, and set properties
set sfp_axi_gpio
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 sfp_axi_gpio
]
...
...
@@ -2180,6 +2183,7 @@ proc create_root_design { parentCell } {
connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI
[
get_bd_intf_pins axi_interconnect_0/M02_AXI
]
[
get_bd_intf_pins pll_gm/S_AXI
]
connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI
[
get_bd_intf_pins axi_iic_si549/S_AXI
]
[
get_bd_intf_pins axi_interconnect_0/M03_AXI
]
connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI
[
get_bd_intf_pins axi_gpio_0/S_AXI
]
[
get_bd_intf_pins axi_interconnect_0/M04_AXI
]
connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI
[
get_bd_intf_pins axi_interconnect_0/M05_AXI
]
[
get_bd_intf_pins wrcore_1g_fmc_0/S_AXI_REGS
]
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD
[
get_bd_intf_pins axi_interconnect_0/S00_AXI
]
[
get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD
]
# Create port connections
...
...
@@ -2211,7 +2215,7 @@ proc create_root_design { parentCell } {
connect_bd_net -net clk_125_p_1
[
get_bd_ports clk_125_p
]
[
get_bd_pins wrcore_1g_fmc_0/clk_125mhz_p_i
]
connect_bd_net -net clk_300_n_1
[
get_bd_ports clk_300_n
]
[
get_bd_pins util_ds_buf_2/IBUF_DS_N
]
connect_bd_net -net clk_300_p_1
[
get_bd_ports clk_300_p
]
[
get_bd_pins util_ds_buf_2/IBUF_DS_P
]
connect_bd_net -net clk_wiz_0_clk_out2
[
get_bd_pins
clk_wiz_0/clk_out2
]
[
get_bd_pins wrcore_1g_fmc_0/clk_sys_i
]
connect_bd_net -net clk_wiz_0_clk_out2
[
get_bd_pins
axi_interconnect_0/M05_ACLK
]
[
get_bd_pins clk_wiz_0/clk_out2
]
[
get_bd_pins rst_ps9/slowest_sync_clk
]
[
get_bd_pins wrcore_1g_fmc_0/clk_sys_i
]
connect_bd_net -net dac_controller_1_dac_cs_n_o
[
get_bd_ports pll_gm_csb
]
[
get_bd_pins pll_gm/pll_gm_csb
]
connect_bd_net -net dac_controller_1_dac_sclk_o
[
get_bd_ports pll_gm_sck
]
[
get_bd_pins pll_gm/pll_gm_sck
]
connect_bd_net -net dac_controller_1_dac_sdata_o
[
get_bd_ports pll_gm_sdi
]
[
get_bd_pins pll_gm/pll_gm_sdi
]
...
...
@@ -2238,6 +2242,7 @@ proc create_root_design { parentCell } {
connect_bd_net -net reset_or_Res
[
get_bd_pins reset_or/Res
]
[
get_bd_pins wrcore_1g_fmc_0/button_rst_i
]
connect_bd_net -net rst_ps8_0_49M_peripheral_aresetn
[
get_bd_pins HMC/s_axi_aresetn
]
[
get_bd_pins axi_gpio_0/s_axi_aresetn
]
[
get_bd_pins axi_iic_si549/s_axi_aresetn
]
[
get_bd_pins axi_interconnect_0/M00_ARESETN
]
[
get_bd_pins axi_interconnect_0/M01_ARESETN
]
[
get_bd_pins axi_interconnect_0/M02_ARESETN
]
[
get_bd_pins axi_interconnect_0/M03_ARESETN
]
[
get_bd_pins axi_interconnect_0/M04_ARESETN
]
[
get_bd_pins axi_interconnect_0/S00_ARESETN
]
[
get_bd_pins pll_gm/S_AXI_ARESETN
]
[
get_bd_pins rst_ps8/peripheral_aresetn
]
[
get_bd_pins sfp_axi_gpio/s_axi_aresetn
]
connect_bd_net -net rst_ps8_interconnect_aresetn
[
get_bd_pins axi_interconnect_0/ARESETN
]
[
get_bd_pins rst_ps8/interconnect_aresetn
]
connect_bd_net -net rst_ps9_peripheral_aresetn
[
get_bd_pins axi_interconnect_0/M05_ARESETN
]
[
get_bd_pins rst_ps9/peripheral_aresetn
]
connect_bd_net -net sfp_axi_gpio_gpio_io_o
[
get_bd_pins HMC/Din
]
[
get_bd_pins pll_gm/Din
]
[
get_bd_pins sfp_axi_gpio/gpio_io_o
]
[
get_bd_pins xlslice_0/Din
]
[
get_bd_pins xlslice_3/Din
]
connect_bd_net -net sfp_detect_1
[
get_bd_ports sfp_detect
]
[
get_bd_pins wrcore_1g_fmc_0/gtp0_mod_def0_b
]
[
get_bd_pins xlconcat_0/In0
]
connect_bd_net -net sfp_los_tx_fault_1
[
get_bd_ports sfp_los_tx_fault
]
[
get_bd_pins wrcore_1g_fmc_0/gtp0_tx_fault_i
]
[
get_bd_pins xlconcat_0/In1
]
...
...
@@ -2271,7 +2276,7 @@ proc create_root_design { parentCell } {
connect_bd_net -net xlslice_0_Dout
[
get_bd_ports sfp_tx_disable
]
[
get_bd_pins xlslice_0/Dout
]
connect_bd_net -net xlslice_3_Dout
[
get_bd_ports term_en
]
[
get_bd_pins xlslice_3/Dout
]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0
[
get_bd_ports PMOD0_3
]
[
get_bd_pins HMC/s_axi_aclk
]
[
get_bd_pins axi_gpio_0/s_axi_aclk
]
[
get_bd_pins axi_iic_si549/s_axi_aclk
]
[
get_bd_pins axi_interconnect_0/ACLK
]
[
get_bd_pins axi_interconnect_0/M00_ACLK
]
[
get_bd_pins axi_interconnect_0/M01_ACLK
]
[
get_bd_pins axi_interconnect_0/M02_ACLK
]
[
get_bd_pins axi_interconnect_0/M03_ACLK
]
[
get_bd_pins axi_interconnect_0/M04_ACLK
]
[
get_bd_pins axi_interconnect_0/S00_ACLK
]
[
get_bd_pins clk_wiz_0/clk_out1
]
[
get_bd_pins pll_gm/S_AXI_ACLK
]
[
get_bd_pins rst_ps8/slowest_sync_clk
]
[
get_bd_pins sfp_axi_gpio/s_axi_aclk
]
[
get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk
]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0
[
get_bd_pins rst_ps8/ext_reset_in
]
[
get_bd_pins zynq_ultra_ps_e_0/pl_resetn0
]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0
[
get_bd_pins rst_ps8/ext_reset_in
]
[
get_bd_pins
rst_ps9/ext_reset_in
]
[
get_bd_pins
zynq_ultra_ps_e_0/pl_resetn0
]
# Create address segments
create_bd_addr_seg -range 0x00001000 -offset 0xA0007000
[
get_bd_addr_spaces zynq_ultra_ps_e_0/Data
]
[
get_bd_addr_segs axi_gpio_0/S_AXI/Reg
]
SEG_axi_gpio_0_Reg
...
...
@@ -2279,6 +2284,7 @@ proc create_root_design { parentCell } {
create_bd_addr_seg -range 0x00010000 -offset 0xA0010000
[
get_bd_addr_spaces zynq_ultra_ps_e_0/Data
]
[
get_bd_addr_segs HMC/axi_quad_spi_0/AXI_LITE/Reg
]
SEG_axi_quad_spi_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0xA0020000
[
get_bd_addr_spaces zynq_ultra_ps_e_0/Data
]
[
get_bd_addr_segs pll_gm/axi_quad_spi_0/AXI_LITE/Reg
]
SEG_axi_quad_spi_0_Reg2
create_bd_addr_seg -range 0x00001000 -offset 0xA0003000
[
get_bd_addr_spaces zynq_ultra_ps_e_0/Data
]
[
get_bd_addr_segs sfp_axi_gpio/S_AXI/Reg
]
SEG_sfp_axi_gpio_Reg
create_bd_addr_seg -range 0x01000000 -offset 0xA1000000
[
get_bd_addr_spaces zynq_ultra_ps_e_0/Data
]
[
get_bd_addr_segs wrcore_1g_fmc_0/S_AXI_REGS/reg0
]
SEG_wrcore_1g_fmc_0_reg0
# Restore current instance
...
...
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/component.xml
View file @
b4786303
This diff is collapsed.
Click to expand it.
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/src/axi4_pkg.vhd
0 → 100644
View file @
b4786303
-------------------------------------------------------------------------------
-- Title : AXI4Lite-to-WB bridge package
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : axi4_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
axi4_pkg
is
-- AXI4-Full interface, master output ports, 32 bits
type
t_axi4_full_master_out_32
is
record
ARVALID
:
std_logic
;
AWVALID
:
std_logic
;
BREADY
:
std_logic
;
RREADY
:
std_logic
;
WLAST
:
std_logic
;
WVALID
:
std_logic
;
ARID
:
std_logic_vector
(
11
downto
0
);
AWID
:
std_logic_vector
(
11
downto
0
);
WID
:
std_logic_vector
(
11
downto
0
);
ARBURST
:
std_logic_vector
(
1
downto
0
);
ARLOCK
:
std_logic_vector
(
1
downto
0
);
ARSIZE
:
std_logic_vector
(
2
downto
0
);
AWBURST
:
std_logic_vector
(
1
downto
0
);
AWLOCK
:
std_logic_vector
(
1
downto
0
);
AWSIZE
:
std_logic_vector
(
2
downto
0
);
ARPROT
:
std_logic_vector
(
2
downto
0
);
AWPROT
:
std_logic_vector
(
2
downto
0
);
ARADDR
:
std_logic_vector
(
31
downto
0
);
AWADDR
:
std_logic_vector
(
31
downto
0
);
WDATA
:
std_logic_vector
(
31
downto
0
);
ARCACHE
:
std_logic_vector
(
3
downto
0
);
ARLEN
:
std_logic_vector
(
3
downto
0
);
ARQOS
:
std_logic_vector
(
3
downto
0
);
AWCACHE
:
std_logic_vector
(
3
downto
0
);
AWLEN
:
std_logic_vector
(
3
downto
0
);
AWQOS
:
std_logic_vector
(
3
downto
0
);
WSTRB
:
std_logic_vector
(
3
downto
0
);
end
record
;
-- AXI4-Full interface, master input ports, 32 bits
type
t_axi4_full_master_in_32
is
record
ARREADY
:
std_logic
;
AWREADY
:
std_logic
;
BVALID
:
std_logic
;
RLAST
:
std_logic
;
RVALID
:
std_logic
;
WREADY
:
std_logic
;
BID
:
std_logic_vector
(
11
downto
0
);
RID
:
std_logic_vector
(
11
downto
0
);
BRESP
:
std_logic_vector
(
1
downto
0
);
RRESP
:
std_logic_vector
(
1
downto
0
);
RDATA
:
std_logic_vector
(
31
downto
0
);
end
record
;
-- AXI4-Lite interface, master output ports, 32 bits
type
t_axi4_lite_master_out_32
is
record
ARVALID
:
std_logic
;
AWVALID
:
std_logic
;
BREADY
:
std_logic
;
RREADY
:
std_logic
;
WLAST
:
std_logic
;
WVALID
:
std_logic
;
ARADDR
:
std_logic_vector
(
31
downto
0
);
AWADDR
:
std_logic_vector
(
31
downto
0
);
WDATA
:
std_logic_vector
(
31
downto
0
);
WSTRB
:
std_logic_vector
(
3
downto
0
);
end
record
;
-- AXI4-Lite interface, master input ports, 32 bits
type
t_axi4_lite_master_in_32
is
record
ARREADY
:
std_logic
;
AWREADY
:
std_logic
;
BVALID
:
std_logic
;
RLAST
:
std_logic
;
RVALID
:
std_logic
;
WREADY
:
std_logic
;
BRESP
:
std_logic_vector
(
1
downto
0
);
RRESP
:
std_logic_vector
(
1
downto
0
);
RDATA
:
std_logic_vector
(
31
downto
0
);
end
record
;
constant
c_axi4_lite_default_master_in_32
:
t_axi4_lite_master_in_32
:
=
(
AWREADY
=>
'0'
,
ARREADY
=>
'0'
,
BVALID
=>
'0'
,
RLAST
=>
'0'
,
RVALID
=>
'0'
,
WREADY
=>
'0'
,
BRESP
=>
"00"
,
RRESP
=>
"00"
,
RDATA
=>
(
others
=>
'0'
)
);
constant
c_axi4_lite_default_master_out_32
:
t_axi4_lite_master_out_32
:
=
(
ARVALID
=>
'0'
,
AWVALID
=>
'0'
,
BREADY
=>
'0'
,
RREADY
=>
'0'
,
WLAST
=>
'0'
,
WVALID
=>
'0'
,
ARADDR
=>
(
others
=>
'0'
),
AWADDR
=>
(
others
=>
'0'
),
WDATA
=>
(
others
=>
'0'
),
WSTRB
=>
(
others
=>
'0'
)
);
subtype
t_axi4_lite_slave_in_32
is
t_axi4_lite_master_out_32
;
subtype
t_axi4_lite_slave_out_32
is
t_axi4_lite_master_in_32
;
constant
c_AXI4_RESP_OKAY
:
std_logic_vector
(
1
downto
0
)
:
=
"00"
;
constant
c_AXI4_RESP_EXOKAY
:
std_logic_vector
(
1
downto
0
)
:
=
"01"
;
constant
c_AXI4_RESP_SLVERR
:
std_logic_vector
(
1
downto
0
)
:
=
"10"
;
constant
c_AXI4_RESP_DECERR
:
std_logic_vector
(
1
downto
0
)
:
=
"11"
;
function
f_axi4_full_to_lite
(
f
:
t_axi4_full_master_out_32
)
return
t_axi4_lite_master_out_32
;
function
f_axi4_lite_to_full
(
l
:
t_axi4_lite_master_in_32
)
return
t_axi4_full_master_in_32
;
component
xwb_axi4lite_bridge
is
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
axi4_slave_i
:
in
t_axi4_lite_slave_in_32
;
axi4_slave_o
:
out
t_axi4_lite_slave_out_32
;
wb_master_o
:
out
t_wishbone_master_out
;
wb_master_i
:
in
t_wishbone_master_in
);
end
component
xwb_axi4lite_bridge
;
component
wb_axi4lite_bridge
is
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
ARVALID
:
in
std_logic
;
AWVALID
:
in
std_logic
;
BREADY
:
in
std_logic
;
RREADY
:
in
std_logic
;
WLAST
:
in
std_logic
;
WVALID
:
in
std_logic
;
ARADDR
:
in
std_logic_vector
(
31
downto
0
);
AWADDR
:
in
std_logic_vector
(
31
downto
0
);
WDATA
:
in
std_logic_vector
(
31
downto
0
);
WSTRB
:
in
std_logic_vector
(
3
downto
0
);
ARREADY
:
out
std_logic
;
AWREADY
:
out
std_logic
;
BVALID
:
out
std_logic
;
RLAST
:
out
std_logic
;
RVALID
:
out
std_logic
;
WREADY
:
out
std_logic
;
BRESP
:
out
std_logic_vector
(
1
downto
0
);
RRESP
:
out
std_logic_vector
(
1
downto
0
);
RDATA
:
out
std_logic_vector
(
31
downto
0
);
wb_adr
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_dat_m2s
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_sel
:
out
std_logic_vector
(
c_wishbone_data_width
/
8-1
downto
0
);
wb_cyc
:
out
std_logic
;
wb_stb
:
out
std_logic
;
wb_we
:
out
std_logic
;
wb_dat_s2m
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_err
:
in
std_logic
:
=
'0'
;
wb_rty
:
in
std_logic
:
=
'0'
;
wb_ack
:
in
std_logic
;
wb_stall
:
in
std_logic
);
end
component
;
-- AXI4-Full interface, master output ports, 512 bits
type
t_axi4_full_master_out_512
is
record
ARVALID
:
std_logic
;
AWVALID
:
std_logic
;
BREADY
:
std_logic
;
RREADY
:
std_logic
;
WLAST
:
std_logic
;
WVALID
:
std_logic
;
ARID
:
std_logic_vector
(
11
downto
0
);
AWID
:
std_logic_vector
(
11
downto
0
);
ARBURST
:
std_logic_vector
(
1
downto
0
);
ARLOCK
:
std_logic
;
ARSIZE
:
std_logic_vector
(
2
downto
0
);
AWBURST
:
std_logic_vector
(
1
downto
0
);
AWLOCK
:
std_logic
;
AWSIZE
:
std_logic_vector
(
2
downto
0
);
ARPROT
:
std_logic_vector
(
2
downto
0
);
AWPROT
:
std_logic_vector
(
2
downto
0
);
ARADDR
:
std_logic_vector
(
31
downto
0
);
AWADDR
:
std_logic_vector
(
31
downto
0
);
WDATA
:
std_logic_vector
(
511
downto
0
);
ARCACHE
:
std_logic_vector
(
3
downto
0
);
ARLEN
:
std_logic_vector
(
7
downto
0
);
ARQOS
:
std_logic_vector
(
3
downto
0
);
AWCACHE
:
std_logic_vector
(
3
downto
0
);
AWLEN
:
std_logic_vector
(
7
downto
0
);
AWQOS
:
std_logic_vector
(
3
downto
0
);
WSTRB
:
std_logic_vector
(
31
downto
0
);
end
record
;
-- AXI4-Full interface, master input ports, 512 bits
type
t_axi4_full_master_in_512
is
record
ARREADY
:
std_logic
;
AWREADY
:
std_logic
;
BVALID
:
std_logic
;
RLAST
:
std_logic
;
RVALID
:
std_logic
;
WREADY
:
std_logic
;
BID
:
std_logic_vector
(
11
downto
0
);
RID
:
std_logic_vector
(
11
downto
0
);
BRESP
:
std_logic_vector
(
1
downto
0
);
RRESP
:
std_logic_vector
(
1
downto
0
);
RDATA
:
std_logic_vector
(
511
downto
0
);
end
record
;
end
package
;
package
body
axi4_pkg
is
function
f_axi4_full_to_lite
(
f
:
t_axi4_full_master_out_32
)
return
t_axi4_lite_master_out_32
is
variable
l
:
t_axi4_lite_master_out_32
;
begin
l
.
ARVALID
:
=
f
.
ARVALID
;
l
.
AWVALID
:
=
f
.
AWVALID
;
l
.
BREADY
:
=
f
.
BREADY
;
l
.
RREADY
:
=
f
.
RREADY
;
l
.
WLAST
:
=
f
.
WLAST
;
l
.
WVALID
:
=
f
.
WVALID
;
l
.
ARADDR
:
=
f
.
ARADDR
;
l
.
AWADDR
:
=
f
.
AWADDR
;
l
.
WDATA
:
=
f
.
WDATA
;
l
.
WSTRB
:
=
f
.
WSTRB
;
return
l
;
end
f_axi4_full_to_lite
;
function
f_axi4_lite_to_full
(
l
:
t_axi4_lite_master_in_32
)
return
t_axi4_full_master_in_32
is
variable
f
:
t_axi4_full_master_in_32
;
begin
f
.
ARREADY
:
=
l
.
ARREADY
;
f
.
AWREADY
:
=
l
.
AWREADY
;
f
.
BVALID
:
=
l
.
BVALID
;
f
.
RLAST
:
=
l
.
RLAST
;
f
.
RVALID
:
=
l
.
RVALID
;
f
.
WREADY
:
=
l
.
WREADY
;
f
.
BID
:
=
(
others
=>
'0'
);
f
.
RID
:
=
(
others
=>
'0'
);
f
.
BRESP
:
=
l
.
BRESP
;
f
.
RRESP
:
=
l
.
RRESP
;
f
.
RDATA
:
=
l
.
RDATA
;
return
f
;
end
f_axi4_lite_to_full
;
end
package
body
;
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/src/wb_axi4lite_bridge.vhd
0 → 100644
View file @
b4786303
-------------------------------------------------------------------------------
-- Title : AXI4Lite-to-WB bridge
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : wb_axi4lite_bridge.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
axi4_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
wb_axi4lite_bridge
is
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
ARVALID
:
in
std_logic
;
AWVALID
:
in
std_logic
;
BREADY
:
in
std_logic
;
RREADY
:
in
std_logic
;
WLAST
:
in
std_logic
:
=
'1'
;
WVALID
:
in
std_logic
;
ARADDR
:
in
std_logic_vector
(
31
downto
0
);
AWADDR
:
in
std_logic_vector
(
31
downto
0
);
WDATA
:
in
std_logic_vector
(
31
downto
0
);
WSTRB
:
in
std_logic_vector
(
3
downto
0
);
ARREADY
:
out
std_logic
;
AWREADY
:
out
std_logic
;
BVALID
:
out
std_logic
;
RLAST
:
out
std_logic
;
RVALID
:
out
std_logic
;
WREADY
:
out
std_logic
;
BRESP
:
out
std_logic_vector
(
1
downto
0
);
RRESP
:
out
std_logic_vector
(
1
downto
0
);
RDATA
:
out
std_logic_vector
(
31
downto
0
);
wb_adr
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_dat_m2s
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_sel
:
out
std_logic_vector
(
c_wishbone_data_width
/
8-1
downto
0
);
wb_cyc
:
out
std_logic
;
wb_stb
:
out
std_logic
;
wb_we
:
out
std_logic
;
wb_dat_s2m
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_err
:
in
std_logic
:
=
'0'
;
wb_rty
:
in
std_logic
:
=
'0'
;
wb_ack
:
in
std_logic
;
wb_stall
:
in
std_logic
);
end
wb_axi4lite_bridge
;
architecture
rtl
of
wb_axi4lite_bridge
is
signal
axi_in
:
t_axi4_lite_master_out_32
;
signal
axi_out
:
t_axi4_lite_master_in_32
;
signal
wb_in
:
t_wishbone_master_in
;
signal
wb_out
:
t_wishbone_master_out
;
begin
axi_in
.
ARVALID
<=
ARVALID
;
axi_in
.
AWVALID
<=
AWVALID
;
axi_in
.
BREADY
<=
BREADY
;
axi_in
.
RREADY
<=
RREADY
;
axi_in
.
WLAST
<=
WLAST
;
axi_in
.
WVALID
<=
WVALID
;
axi_in
.
ARADDR
<=
ARADDR
;
axi_in
.
AWADDR
<=
AWADDR
;
axi_in
.
WDATA
<=
WDATA
;
axi_in
.
WSTRB
<=
WSTRB
;
ARREADY
<=
axi_out
.
ARREADY
;
AWREADY
<=
axi_out
.
AWREADY
;
BVALID
<=
axi_out
.
BVALID
;
RLAST
<=
axi_out
.
RLAST
;
RVALID
<=
axi_out
.
RVALID
;
WREADY
<=
axi_out
.
WREADY
;
BRESP
<=
axi_out
.
BRESP
;
RRESP
<=
axi_out
.
RRESP
;
RDATA
<=
axi_out
.
RDATA
;
wb_adr
<=
wb_out
.
adr
;
wb_dat_m2s
<=
wb_out
.
dat
;
wb_stb
<=
wb_out
.
stb
;
wb_sel
<=
wb_out
.
sel
;
wb_cyc
<=
wb_out
.
cyc
;
wb_we
<=
wb_out
.
we
;
wb_in
.
err
<=
wb_err
;
wb_in
.
rty
<=
wb_rty
;
wb_in
.
ack
<=
wb_ack
;
wb_in
.
stall
<=
wb_stall
;
wb_in
.
dat
<=
wb_dat_s2m
;
U_Wrapped_Bridge
:
xwb_axi4lite_bridge
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
axi4_slave_i
=>
axi_in
,
axi4_slave_o
=>
axi_out
,
wb_master_o
=>
wb_out
,
wb_master_i
=>
wb_in
);
end
rtl
;
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/src/xwb_axi4lite_bridge.vhd
0 → 100644
View file @
b4786303
-------------------------------------------------------------------------------
-- Title : AXI4Lite-to-WB bridge wrapper
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : xwb_axi4lite_bridge.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
axi4_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
xwb_axi4lite_bridge
is
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
axi4_slave_i
:
in
t_axi4_lite_slave_in_32
;
axi4_slave_o
:
out
t_axi4_lite_slave_out_32
;
wb_master_o
:
out
t_wishbone_master_out
;
wb_master_i
:
in
t_wishbone_master_in
);
end
xwb_axi4lite_bridge
;
architecture
rtl
of
xwb_axi4lite_bridge
is
constant
c_timeout
:
integer
:
=
256
;
type
t_state
is
(
IDLE
,
ISSUE_WRITE
,
ISSUE_READ
,
COMPLETE_WRITE
,
COMPLETE_READ
,
WAIT_ACK_READ
,
WAIT_ACK_WRITE
,
RESPONSE_READ
,
RESPONSE_WRITE
);
signal
state
:
t_state
;
signal
count
:
unsigned
(
10
downto
0
);
begin
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
axi4_slave_o
<=
c_axi4_lite_default_master_in_32
;
wb_master_o
.
cyc
<=
'0'
;
state
<=
IDLE
;
else
case
state
is
when
IDLE
=>
wb_master_o
.
cyc
<=
'0'
;
axi4_slave_o
.
ARREADY
<=
'1'
;
axi4_slave_o
.
AWREADY
<=
'1'
;
axi4_slave_o
.
WREADY
<=
'0'
;
axi4_slave_o
.
BVALID
<=
'0'
;
axi4_slave_o
.
BRESP
<=
(
others
=>
'X'
);
axi4_slave_o
.
RDATA
<=
(
others
=>
'X'
);
axi4_slave_o
.
RRESP
<=
(
others
=>
'X'
);
axi4_slave_o
.
RVALID
<=
'0'
;
axi4_slave_o
.
RLAST
<=
'0'
;
if
(
axi4_slave_i
.
AWVALID
=
'1'
)
then
state
<=
ISSUE_WRITE
;
wb_master_o
.
adr
<=
axi4_slave_i
.
AWADDR
;
elsif
(
axi4_slave_i
.
ARVALID
=
'1'
)
then
state
<=
ISSUE_READ
;
wb_master_o
.
adr
<=
axi4_slave_i
.
ARADDR
;
end
if
;
when
ISSUE_WRITE
=>
wb_master_o
.
cyc
<=
'1'
;
wb_master_o
.
we
<=
'1'
;
axi4_slave_o
.
WREADY
<=
'1'
;
if
(
axi4_slave_i
.
WVALID
=
'1'
)
then
wb_master_o
.
stb
<=
'1'
;
wb_master_o
.
sel
<=
axi4_slave_i
.
WSTRB
;
wb_master_o
.
dat
<=
axi4_slave_i
.
WDATA
;
state
<=
COMPLETE_WRITE
;
end
if
;
when
ISSUE_READ
=>
wb_master_o
.
cyc
<=
'1'
;
wb_master_o
.
stb
<=
'1'
;
wb_master_o
.
we
<=
'0'
;
axi4_slave_o
.
RVALID
<=
'0'
;
axi4_slave_o
.
RLAST
<=
'0'
;
state
<=
COMPLETE_READ
;
when
COMPLETE_READ
=>
if
(
wb_master_i
.
stall
=
'0'
)
then
wb_master_o
.
stb
<=
'0'
;
if
(
wb_master_i
.
ack
=
'1'
)
then
state
<=
IDLE
;
axi4_slave_o
.
RRESP
<=
c_AXI4_RESP_OKAY
;
axi4_slave_o
.
RDATA
<=
wb_master_i
.
dat
;
axi4_slave_o
.
RVALID
<=
'1'
;
axi4_slave_o
.
RLAST
<=
'1'
;
wb_master_o
.
cyc
<=
'0'
;
else
state
<=
WAIT_ACK_READ
;
count
<=
(
others
=>
'0'
);
end
if
;
end
if
;
when
COMPLETE_WRITE
=>
if
(
wb_master_i
.
stall
=
'0'
)
then
wb_master_o
.
stb
<=
'0'
;
if
(
wb_master_i
.
ack
=
'1'
)
then
state
<=
RESPONSE_WRITE
;
axi4_slave_o
.
BVALID
<=
'1'
;
axi4_slave_o
.
BRESP
<=
c_AXI4_RESP_OKAY
;
wb_master_o
.
cyc
<=
'0'
;
else
state
<=
WAIT_ACK_WRITE
;
count
<=
(
others
=>
'0'
);
end
if
;
end
if
;
when
WAIT_ACK_WRITE
=>
if
(
wb_master_i
.
ack
=
'1'
)
then
state
<=
RESPONSE_WRITE
;
axi4_slave_o
.
BVALID
<=
'1'
;
axi4_slave_o
.
BRESP
<=
c_AXI4_RESP_OKAY
;
wb_master_o
.
cyc
<=
'0'
;
elsif
count
=
c_timeout
then
state
<=
RESPONSE_WRITE
;
axi4_slave_o
.
BVALID
<=
'1'
;
axi4_slave_o
.
BRESP
<=
c_AXI4_RESP_SLVERR
;
wb_master_o
.
cyc
<=
'0'
;
end
if
;
count
<=
count
+
1
;
when
WAIT_ACK_READ
=>
if
(
wb_master_i
.
ack
=
'1'
)
then
state
<=
RESPONSE_READ
;
axi4_slave_o
.
RRESP
<=
c_AXI4_RESP_OKAY
;
axi4_slave_o
.
RVALID
<=
'1'
;
axi4_slave_o
.
RLAST
<=
'1'
;
axi4_slave_o
.
RDATA
<=
wb_master_i
.
dat
;
wb_master_o
.
cyc
<=
'0'
;
elsif
count
=
c_timeout
then
state
<=
RESPONSE_READ
;
axi4_slave_o
.
RRESP
<=
c_AXI4_RESP_SLVERR
;
axi4_slave_o
.
RVALID
<=
'1'
;
axi4_slave_o
.
RLAST
<=
'1'
;
axi4_slave_o
.
RDATA
<=
(
others
=>
'X'
);
wb_master_o
.
cyc
<=
'0'
;
end
if
;
count
<=
count
+
1
;
when
RESPONSE_WRITE
=>
if
(
axi4_slave_i
.
BREADY
=
'1'
)
then
axi4_slave_o
.
BVALID
<=
'0'
;
state
<=
IDLE
;
end
if
;
when
RESPONSE_READ
=>
if
(
axi4_slave_i
.
RREADY
=
'1'
)
then
axi4_slave_o
.
RVALID
<=
'0'
;
state
<=
IDLE
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
end
rtl
;
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/src/zcu102.vhd
View file @
b4786303
...
...
@@ -16,6 +16,8 @@ use UNISIM.vcomponents.all;
library
work
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
axi4_pkg
.
all
;
entity
zcu102
is
generic
(
...
...
@@ -119,7 +121,30 @@ entity zcu102 is
-- Voltage converter enabling pin
voltage_conv_en_o
:
out
std_logic
;
clk_125mhz_o
:
out
std_logic
clk_125mhz_o
:
out
std_logic
;
-- System registers access (AXI4Lite-Slave)
S_AXI_REGS_arvalid
:
in
std_logic
;
S_AXI_REGS_awvalid
:
in
std_logic
;
S_AXI_REGS_bready
:
in
std_logic
;
S_AXI_REGS_rready
:
in
std_logic
;
S_AXI_REGS_wlast
:
in
std_logic
:
=
'1'
;
S_AXI_REGS_wvalid
:
in
std_logic
;
S_AXI_REGS_araddr
:
in
std_logic_vector
(
31
downto
0
);
S_AXI_REGS_awaddr
:
in
std_logic_vector
(
31
downto
0
);
S_AXI_REGS_wdata
:
in
std_logic_vector
(
31
downto
0
);
S_AXI_REGS_wstrb
:
in
std_logic_vector
(
3
downto
0
);
S_AXI_REGS_arready
:
out
std_logic
;
S_AXI_REGS_awready
:
out
std_logic
;
S_AXI_REGS_bvalid
:
out
std_logic
;
S_AXI_REGS_rlast
:
out
std_logic
;
S_AXI_REGS_rvalid
:
out
std_logic
;
S_AXI_REGS_wready
:
out
std_logic
;
S_AXI_REGS_bresp
:
out
std_logic_vector
(
1
downto
0
);
S_AXI_REGS_rresp
:
out
std_logic_vector
(
1
downto
0
);
S_AXI_REGS_rdata
:
out
std_logic_vector
(
31
downto
0
)
);
end
zcu102
;
...
...
@@ -162,6 +187,7 @@ component wr_gth_phy_kintex7ultrascale
pad_rxp_i
:
in
std_logic
:
=
'0'
;
rdy_o
:
out
std_logic
);
end
component
;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
...
...
@@ -282,8 +308,48 @@ component wr_gth_phy_kintex7ultrascale
signal
s_sync
:
std_logic
;
signal
wb_master_in
:
t_wishbone_master_in
;
signal
wb_master_out
:
t_wishbone_master_out
;
begin
U_axi4lite_bridge
:
wb_axi4lite_bridge
port
map
(
clk_sys_i
=>
clk_sys
,
rst_n_i
=>
local_reset_n
,
ARVALID
=>
S_AXI_REGS_arvalid
,
AWVALID
=>
S_AXI_REGS_awvalid
,
BREADY
=>
S_AXI_REGS_bready
,
RREADY
=>
S_AXI_REGS_rready
,
WLAST
=>
S_AXI_REGS_wlast
,
WVALID
=>
S_AXI_REGS_wvalid
,
ARADDR
=>
S_AXI_REGS_araddr
,
AWADDR
=>
S_AXI_REGS_awaddr
,
WDATA
=>
S_AXI_REGS_wdata
,
WSTRB
=>
S_AXI_REGS_wstrb
,
ARREADY
=>
S_AXI_REGS_arready
,
AWREADY
=>
S_AXI_REGS_awready
,
BVALID
=>
S_AXI_REGS_bvalid
,
RLAST
=>
S_AXI_REGS_rlast
,
RVALID
=>
S_AXI_REGS_rvalid
,
WREADY
=>
S_AXI_REGS_wready
,
BRESP
=>
S_AXI_REGS_bresp
,
RRESP
=>
S_AXI_REGS_rresp
,
RDATA
=>
S_AXI_REGS_rdata
,
wb_adr
=>
wb_master_out
.
adr
,
wb_dat_m2s
=>
wb_master_out
.
dat
,
wb_sel
=>
wb_master_out
.
sel
,
wb_cyc
=>
wb_master_out
.
cyc
,
wb_stb
=>
wb_master_out
.
stb
,
wb_we
=>
wb_master_out
.
we
,
wb_dat_s2m
=>
wb_master_in
.
dat
,
wb_err
=>
wb_master_in
.
err
,
wb_rty
=>
wb_master_in
.
rty
,
wb_ack
=>
wb_master_in
.
ack
,
wb_stall
=>
wb_master_in
.
stall
);
-- PLL stuff
pllout_clk_dmtd
<=
clk_25m_vcxo_bufg
;
...
...
@@ -436,7 +502,7 @@ begin
g_interface_mode
=>
c_interface_mode
,
g_address_granularity
=>
c_address_granularity
,
g_aux_sdb
=>
c_wrc_periph3_sdb
,
g_softpll_enable_debugger
=>
fals
e
,
g_softpll_enable_debugger
=>
tru
e
,
g_vuart_fifo_size
=>
1024
)
port
map
(
clk_sys_i
=>
clk_sys
,
...
...
@@ -498,8 +564,8 @@ begin
owr_pwren_o
=>
open
,
owr_en_o
=>
owr_en
,
owr_i
=>
owr_i
,
slave_i
=>
cc_dummy_slave_in
,
slave_o
=>
ope
n
,
slave_i
=>
wb_master_out
,
slave_o
=>
wb_master_i
n
,
aux_master_o
=>
open
,
aux_master_i
=>
cc_dummy_master_in
,
wrf_src_o
=>
open
,
...
...
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