White Rabbit Switch Hardware version 4
Project description
This project describes the development of the hardware of version 4 of the White Rabbit Switch.
The White Rabbit Switch is an open hardware design of an Ethernet switch licensed under CERN OHL 1.2. It is a central element of a White Rabbit network and is designed as a part of the White Rabbit project.
Possible design with hot-swappable fans and redundant PSU with basic enclosure
Project milestones
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Preliminary study of features, components, requirements:
- Preliminary study of input from the WR community, CERN IT
- In-depth study of WRS-v4/18 features by SevenSolutions
- Analysis of resource utilization for the candidate FPGA choice by Creotech
- Verification of 1Gb and 10Gb transceiver in the chosen FPGA/family - ongoing
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Proposal of WRS-v4/18 architecture - to be completed in Q1 of 2020 by SevenSolutions
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Request for comments/feedback from the WR community - Q1 2020
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Design/production of HW prototype - 2020
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Port of HDL/SW from WRS-v3/18 to the WRS-v4/18 for 1Gb only - 2021 or later
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Upgrade of HDL/SW to 10Gb
Contacts
Commercial producers
- WRS V4 under design, to be produced by Seven Solutions
Commercial partners involved:
General question about project
- Maciej Lipinski - CERN
Status
| Date | Event |
|---|---|
| 07-03-2014 | First ideas of a next generation WRS with one or more 10 Gbps ports |
| 01-07-2016 | First collection of requirements for V4 generation switch requested on wr-dev mailing list (archive) |
| 07-10-2018 | Second collection of requirements for V4 generation switch made on the 10th WR Workshop |
| 30-09-2018 | First "Technical proposal for the design of a new White Rabbit Switch" by Seven Solutions |
| 28-11-2018 |
Seven Solutions ordered to conduct preliminary design study and produce Technical Specification with definition of architecture and key components selection) |
| 11-07-2019 | Preliminary FPGA/CPU choice: ZU11, final decision will be based on the following study in Aug-Sept: - evaluation of required resources to know what size/package of the FPGA to choose - verification of determinism/suitability of the gigabit transceivers (GTH) and noise added by FPGA and its pins. |
| 19-07-2019 | Two ZCU106 Xilinx Evaluation Boards ordered |
| 31-07-2019 | Creotech ordered to perform evaluation of the required resources |
| 31-07-2019 | Meeting with CERN IT experts (see notes) |
| 09-10-2019 | Creotech delivered WRS resource utilisation on Xilinx US+ FPGA |
| 19-10-2019 | Seven Solutions delivered Study on the new hardware features for the WRS-4/18 |