afcz wip

63a4e161 · Tomasz Wlostowski · 59004e8e · 63a4e161 · 63a4e161 · 63a4e161
Commit 63a4e161 authored Jul 16, 2021 by Tomasz Wlostowski
6 changed files
--- a/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+++ b/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2012-01-10
-- Last update: 2020-07-31
+-- Last update: 2020-08-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -154,6 +154,13 @@ entity wrsw_rt_subsystem is
    si57x_scl_i : in std_logic;
    si57x_sda_i : in std_logic;

+    aux_scl_oen_o : out std_logic;
+    aux_sda_oen_o : out std_logic;
+    aux_scl_o : out std_logic;
+    aux_sda_o : out std_logic;
+    aux_scl_i : in std_logic;
+    aux_sda_i : in std_logic;
+    
    -- Debug
    spll_dbg_o : out std_logic_vector(5 downto 0)
    );
@@ -218,7 +225,7 @@ architecture rtl of wrsw_rt_subsystem is
  signal cpu_reset_n : std_logic;

  signal dummy             : std_logic_vector(63 downto 0);
-  signal gpio_out, gpio_in : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0);
+  signal gpio_oen, gpio_out, gpio_in : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0);

  signal dac_out_data, dac_dmtd_data : std_logic_vector(15 downto 0);
  signal dac_out_load, dac_dmtd_load : std_logic;
@@ -457,7 +464,7 @@ begin  -- rtl
      gpio_b     => open,
      gpio_out_o => gpio_out,
      gpio_in_i  => gpio_in,
-      gpio_oen_o => open);
+      gpio_oen_o => gpio_oen);

  U_Timer : xwb_tics
    generic map (
@@ -493,10 +500,19 @@ begin  -- rtl
  pll_reset_n_o <= gpio_out(1);
  cpu_reset_n   <= not gpio_out(2) and rst_sys_n_i;
  rst_n_o       <= gpio_out(3);
+
+
+  
  
  gpio_in(4)          <= ljd_board_detected;
  gpio_in(7 downto 5) <= ljd_osc_freq_i;

+  aux_scl_oen_o <= gpio_oen(8);
+  aux_sda_oen_o <= gpio_oen(9);
+  aux_scl_o <= '0';
+  aux_sda_o <= '0';
+  gpio_in(8) <= aux_scl_i;
+  gpio_in(9) <= aux_sda_i;
  
  dac_main_value_o <= dac_out_data;
  dac_main_load_o <= dac_out_load;

--- a/testbench/zynq_top/main.sv
+++ b/testbench/zynq_top/main.sv
@@ -103,6 +103,14 @@ module main;

      $error("WR!");

+      acc.write('h10304, 'h8);
+      acc.write('h54000, 'haa);
+      acc.read('h54000, rv);
+      $display("Rd(0) %x", rv);
+      $stop;
+      
+      
+      
      for(i=0; i<100; i+=1)
 	acc.write(i*4, i);
      

--- a/testbench/zynq_top/wave.do
+++ b/testbench/zynq_top/wave.do
@@ -451,16 +451,78 @@ add wave -noupdate -group Ep0WB /main/DUT/U_Real_Top/gen_network_stuff/gen_endpo
 add wave -noupdate -group Ep0WB /main/DUT/U_Real_Top/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/rd_int
 add wave -noupdate -group Ep0WB /main/DUT/U_Real_Top/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/allones
 add wave -noupdate -group Ep0WB /main/DUT/U_Real_Top/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/allzeros
-add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/clk_sys_i
-add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/rst_n_i
-add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/axi4_slave_i
-add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/axi4_slave_o
-add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/wb_master_o
-add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/wb_master_i
-add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/state
-add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/count
+add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/clk_sys_i
+add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/rst_n_i
+add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/axi4_slave_i
+add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/axi4_slave_o
+add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/wb_master_o
+add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/wb_master_i
+add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/state
+add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/count
+add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/clk_sys_i
+add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/rst_n_i
+add wave -noupdate -group i2c -expand /main/DUT/U_Real_Top/U_MiniBackplane_I2C/slave_i
+add wave -noupdate -group i2c -expand /main/DUT/U_Real_Top/U_MiniBackplane_I2C/slave_o
+add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/desc_o
+add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/int_o
+add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/scl_pad_i
+add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/scl_pad_o
+add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/scl_padoen_o
+add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/sda_pad_i
+add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/sda_pad_o
+add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/sda_padoen_o
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_clk_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_rst_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/arst_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_adr_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_we_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_stb_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_cyc_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_ack_o
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/inta_o
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_pad_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_pad_o
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_padoen_o
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_pad_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_pad_o
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_padoen_o
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/prer
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/txr
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/rxr
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/cr
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sr
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/rst_i
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_wacc
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/iack_o
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/done
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sta
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sto
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/rd
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wr
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ack
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/iack
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/core_en
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ien
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/irxack
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/rxack
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/tip
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/irq_flag
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/i2c_busy
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/al
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/i2c_al
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_in
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_out
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_oen
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_in
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_out
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_oen
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/if_num
+add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/if_busy
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {12478773 ps} 0}
+WaveRestoreCursors {{Cursor 1} {10721600 ps} 0}
 configure wave -namecolwidth 150
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -475,4 +537,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ps} {32768 ns}
+WaveRestoreZoom {8673600 ps} {12769600 ps}
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
 -- Company    : CERN BE-CO-HT
 -- Created    : 2012-02-21
-- Last update: 2020-07-31
+-- Last update: 2020-08-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -196,7 +196,14 @@ entity scb_top_bare is
    rts_si57x_sda_oen_o : out std_logic;
    rts_si57x_scl_i : in std_logic;
    rts_si57x_sda_i : in std_logic;
-    
+
+    aux_scl_oen_o : out std_logic;
+    aux_sda_oen_o : out std_logic;
+    aux_scl_o : out std_logic;
+    aux_sda_o : out std_logic;
+    aux_scl_i : in std_logic;
+    aux_sda_i : in std_logic;
+
    ---------------------------------------------------------------------------
    -- Mini-backplane PWM fans
    ---------------------------------------------------------------------------
@@ -659,6 +666,13 @@ begin
      si57x_sda_oen_o => rts_si57x_sda_oen_o,
      si57x_scl_i => rts_si57x_scl_i,
      si57x_sda_i => rts_si57x_sda_i,
+
+      aux_scl_i => aux_scl_i,
+      aux_sda_i => aux_sda_i,
+      aux_scl_o => aux_scl_o,
+      aux_sda_o => aux_sda_o,
+      aux_scl_oen_o => aux_scl_oen_o,
+      aux_sda_oen_o => aux_sda_oen_o,
      
      spll_dbg_o    => spll_dbg_o);


--- a/top/zynq_us/scb_8ports/afcz_wrs_8p_top.vhd
+++ b/top/zynq_us/scb_8ports/afcz_wrs_8p_top.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
 -- Company    : CERN BE-CO-HT
 -- Created    : 2012-03-07
-- Last update: 2020-08-09
+-- Last update: 2020-08-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -270,6 +270,8 @@ architecture Behavioral of afcz_wrs_8p_top is

  signal mgtclk1_224, mgtclk1_224_prebuf : std_logic;
  
+  signal aux_scl_oen, aux_sda_oen : std_logic;
+  signal afcz_scl_oen, afcz_sda_oen : std_logic;
  
 begin

@@ -595,6 +597,11 @@ begin
      rts_si57x_scl_i => rts_si57x_scl_in,
      rts_si57x_sda_i => rts_si57x_sda_in,

+      aux_scl_i => i2c_scl_in(0),
+      aux_sda_i => i2c_sda_in(0),
+      aux_scl_oen_o => aux_scl_oen,
+      aux_sda_oen_o => aux_sda_oen,
+      
      rts_gpio_o => rts_gpio_out,
      rts_gpio_i => rts_gpio_in
      
@@ -626,19 +633,22 @@ begin
     T  => rts_si57x_scl_oen);


+  afcz_scl_oen <= i2c_scl_oen(0) and aux_scl_oen;
+  afcz_sda_oen <= i2c_sda_oen(0) and aux_sda_oen;
+  
  IOBUF_3 : IOBUF
   port map (
     O  => i2c_scl_in(0),
     IO => afcz_scl_b,
     I  => i2c_scl_out(0),
-     T => i2c_scl_oen(0) ); 
+     T =>  afcz_scl_oen); 

  IOBUF_4 : IOBUF
   port map (
     O  => i2c_sda_in(0),
     IO => afcz_sda_b,
     I  => i2c_sda_out(0),
-     T => i2c_sda_oen(0) ); 
+     T => afcz_sda_oen ); 

  
  U_WR_DACs : entity work.spec_serial_dac_arb

--- a/top/zynq_us/scb_8ports/timing.xdc
+++ b/top/zynq_us/scb_8ports/timing.xdc