Commit 59004e8e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

10G hacks.

parent 149742fa
Subproject commit dcc7cc33ffa3bce1a9a3da9ea317e3c768830398
Subproject commit f30e69b9634cd6ee4faeca251b3409119050b9d3
Subproject commit faf5e9a346b80c028f03d032130913dacd224cc0
Subproject commit 9a399acd2852c94ec4d147976b0bcca78b6bbd78
......@@ -70,60 +70,60 @@ architecture Behavioral of wrsw_ljd_detect is
begin
clock_divider_inst : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
clk_divider <= clk_divider + 1;
if (clk_divider = g_clk_divider - 1) then
clk_divider <= 0;
clk_en <= '1';
else
clk_en <= '0';
end if;
end if;
end process;
-- clock_divider_inst : process (clk_sys_i)
-- begin
-- if rising_edge (clk_sys_i) then
-- clk_divider <= clk_divider + 1;
-- if (clk_divider = g_clk_divider - 1) then
-- clk_divider <= 0;
-- clk_en <= '1';
-- else
-- clk_en <= '0';
-- end if;
-- end if;
-- end process;
FSM_INST : process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
board_detected_o <= '0';
fsm_state <= INIT;
else
case fsm_state is
when INIT =>
board_detected_o <= '0';
bit_position <= 0;
fsm_state <= WRITE_BIT;
error_detected <= '0';
-- FSM_INST : process (clk_sys_i)
-- begin
-- if rising_edge(clk_sys_i) then
-- if rst_n_i = '0' then
-- board_detected_o <= '0';
-- fsm_state <= INIT;
-- else
-- case fsm_state is
-- when INIT =>
-- board_detected_o <= '0';
-- bit_position <= 0;
-- fsm_state <= WRITE_BIT;
-- error_detected <= '0';
when WRITE_BIT =>
loopback_o <= g_pattern(bit_position);
if (clk_en = '1') then
fsm_state <= READ_BIT;
end if;
-- when WRITE_BIT =>
-- loopback_o <= g_pattern(bit_position);
-- if (clk_en = '1') then
-- fsm_state <= READ_BIT;
-- end if;
when READ_BIT =>
if (g_pattern(bit_position) = loopback_i) then
if (bit_position = g_pattern'length-1) then
fsm_state <= DONE;
else
bit_position <= bit_position + 1;
fsm_state <= WRITE_BIT;
end if;
else
error_detected <= '1';
fsm_state <= DONE;
end if;
-- when READ_BIT =>
-- if (g_pattern(bit_position) = loopback_i) then
-- if (bit_position = g_pattern'length-1) then
-- fsm_state <= DONE;
-- else
-- bit_position <= bit_position + 1;
-- fsm_state <= WRITE_BIT;
-- end if;
-- else
-- error_detected <= '1';
-- fsm_state <= DONE;
-- end if;
when DONE =>
board_detected_o <= not error_detected;
-- when DONE =>
-- board_detected_o <= not error_detected;
when others =>
fsm_state <= INIT;
end case;
end if;
end if;
end process;
-- when others =>
-- fsm_state <= INIT;
-- end case;
-- end if;
-- end if;
-- end process;
end Behavioral;
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2018-11-07
-- Last update: 2020-07-31
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -49,7 +49,8 @@ entity wrsw_rt_subsystem is
g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean;
g_phy_lpcalib : t_bool_array(0 to 17));
g_phy_lpcalib : t_bool_array(0 to 17);
g_with_si57x: boolean := true);
port(
clk_ref_i : in std_logic;
......@@ -78,13 +79,10 @@ entity wrsw_rt_subsystem is
-- PLL DAC Drive
---------------------------------------------------------------------------
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
dac_helper_data_o : out std_logic;
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_helper_load_o : out std_logic;
dac_helper_value_o : out std_logic_vector(15 downto 0);
dac_main_load_o : out std_logic;
dac_main_value_o : out std_logic_vector(15 downto 0);
-- Debug UART
uart_txd_o : out std_logic;
......@@ -109,6 +107,7 @@ entity wrsw_rt_subsystem is
sel_clk_sys_o : out std_logic; -- system clock selection: 0 = startup
-- clock, 1 = PLL clock
-- Wired to IODelay in the top module for precise 1-PPS out alignment
-- with clk_aux
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others => '0');
......@@ -147,6 +146,14 @@ entity wrsw_rt_subsystem is
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
rts_gpio_o : out std_logic_vector(7 downto 0);
rts_gpio_i : in std_logic_vector(7 downto 0);
si57x_scl_oen_o : out std_logic;
si57x_sda_oen_o : out std_logic;
si57x_scl_i : in std_logic;
si57x_sda_i : in std_logic;
-- Debug
spll_dbg_o : out std_logic_vector(5 downto 0)
);
......@@ -182,8 +189,8 @@ architecture rtl of wrsw_rt_subsystem is
-- 0x10300 - 0x10400: GPIO
-- 0x10400 - 0x10500: Timer
constant c_NUM_GPIO_PINS : integer := 9;
constant c_NUM_WB_SLAVES : integer := 9;
constant c_NUM_GPIO_PINS : integer := 32;
constant c_NUM_WB_SLAVES : integer := 10;
constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1;
......@@ -197,6 +204,7 @@ architecture rtl of wrsw_rt_subsystem is
constant c_SLAVE_PPSGEN : integer := 6;
constant c_SLAVE_GEN10 : integer := 7;
constant c_SLAVE_SPI_EXT : integer := 8;
constant c_SLAVE_SI57X : integer := 9;
signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(1 downto 0);
......@@ -214,6 +222,7 @@ architecture rtl of wrsw_rt_subsystem is
signal dac_out_data, dac_dmtd_data : std_logic_vector(15 downto 0);
signal dac_out_load, dac_dmtd_load : std_logic;
signal dac_out_data_ext : std_logic_vector(23 downto 0);
signal clk_rx_vec, clk_rx_sampled_vec : std_logic_vector(g_num_rx_clocks-1 downto 0);
signal pps_csync : std_logic;
......@@ -488,40 +497,12 @@ begin -- rtl
gpio_in(4) <= ljd_board_detected;
gpio_in(7 downto 5) <= ljd_osc_freq_i;
U_Main_DAC : gc_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 0)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
value_i => dac_out_data,
cs_sel_i => "1",
load_i => dac_out_load,
sclk_divsel_i => "010",
dac_cs_n_o(0) => dac_main_sync_n_o,
dac_sclk_o => dac_main_sclk_o,
dac_sdata_o => dac_main_data_o);
U_DMTD_DAC : gc_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 0)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
value_i => dac_dmtd_data,
cs_sel_i => "1",
load_i => dac_dmtd_load,
sclk_divsel_i => "010",
dac_cs_n_o(0) => dac_helper_sync_n_o,
dac_sclk_o => dac_helper_sclk_o,
dac_sdata_o => dac_helper_data_o);
dac_main_value_o <= dac_out_data;
dac_main_load_o <= dac_out_load;
dac_helper_value_o <= dac_dmtd_data;
dac_helper_load_o <= dac_dmtd_load;
------------------------------------------------------
-- WRS Low jitter daughterboard
......@@ -548,5 +529,30 @@ begin -- rtl
ljd_pll_reset_n_o <= not ext_pll_reset when(ljd_board_detected = '1') else
'1';
rts_gpio_o <= gpio_out(31 downto 24);
gpio_in(31 downto 24) <= rts_gpio_i;
gen_with_si57x: if g_with_si57x generate
dac_out_data_ext <= x"00" & dac_out_data;
xwr_si57x_interface_1: entity work.xwr_si57x_interface
generic map (
g_simulation => f_pick(g_simulation, 1, 0 ))
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
tm_dac_value_i => dac_out_data_ext,
tm_dac_value_wr_i => dac_out_load,
scl_pad_oen_o => si57x_scl_oen_o,
sda_pad_oen_o => si57x_sda_oen_o,
scl_pad_i => si57x_scl_i,
sda_pad_i => si57x_sda_i,
slave_i => cnx_master_out(c_SLAVE_SI57X),
slave_o => cnx_master_in(c_SLAVE_SI57X));
end generate gen_with_si57x;
end rtl;
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2014-12-01
-- Last update: 2014-12-01
-- Last update: 2020-07-28
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -218,47 +218,47 @@ begin
rst <= not rst_n_i;
rst_oserdes <= not pll_locked;
U_PLL_500: pll_62_5_500mhz
port map (
clk_ref_i => clk_i,
clk_500_o => clk_500,
CLKFB_IN => clk_fb_buf,
CLKFB_OUT => clk_fb,
RESET => rst,
LOCKED => pll_locked);
U_BUFG: BUFG
port map(
O => clk_fb_buf,
I => clk_fb);
U_BUFG_500: BUFG
port map(
O => clk_500_buf,
I => clk_500);
clk_500_o <= '0'; --clk_500_buf;
U_10MHZ_SERDES: oserdes_8_to_1
generic map(
dev_w => c_DATA_W)
port map(
DATA_OUT_FROM_DEVICE => sd_data,
DATA_OUT_TO_PINS_P => sd_out_p,
DATA_OUT_TO_PINS_N => sd_out_n,
DELAY_RESET => wb_regs_out.ior_tap_set_wr_o,
DELAY_DATA_CE => (others=>'0'),
DELAY_DATA_INC => (others=>'0'),
DELAY_TAP_IN => wb_regs_out.ior_tap_set_o,
DELAY_TAP_OUT => wb_regs_in.ior_tap_cur_i,
DELAY_LOCKED => wb_regs_in.ior_lck_i,
REF_CLOCK => clk_i,
CLK_IN => clk_500_buf,
CLK_DIV_IN => clk_i,
IO_RESET => rst_oserdes);
clk_aux_p_o <= sd_out_p(0);
clk_aux_n_o <= sd_out_n(0);
-- U_PLL_500: pll_62_5_500mhz
-- port map (
-- clk_ref_i => clk_i,
-- clk_500_o => clk_500,
-- CLKFB_IN => clk_fb_buf,
-- CLKFB_OUT => clk_fb,
-- RESET => rst,
-- LOCKED => pll_locked);
-- U_BUFG: BUFG
-- port map(
-- O => clk_fb_buf,
-- I => clk_fb);
-- U_BUFG_500: BUFG
-- port map(
-- O => clk_500_buf,
-- I => clk_500);
-- clk_500_o <= '0'; --clk_500_buf;
-- U_10MHZ_SERDES: oserdes_8_to_1
-- generic map(
-- dev_w => c_DATA_W)
-- port map(
-- DATA_OUT_FROM_DEVICE => sd_data,
-- DATA_OUT_TO_PINS_P => sd_out_p,
-- DATA_OUT_TO_PINS_N => sd_out_n,
-- DELAY_RESET => wb_regs_out.ior_tap_set_wr_o,
-- DELAY_DATA_CE => (others=>'0'),
-- DELAY_DATA_INC => (others=>'0'),
-- DELAY_TAP_IN => wb_regs_out.ior_tap_set_o,
-- DELAY_TAP_OUT => wb_regs_in.ior_tap_cur_i,
-- DELAY_LOCKED => wb_regs_in.ior_lck_i,
-- REF_CLOCK => clk_i,
-- CLK_IN => clk_500_buf,
-- CLK_DIV_IN => clk_i,
-- IO_RESET => rst_oserdes);
-- clk_aux_p_o <= sd_out_p(0);
-- clk_aux_n_o <= sd_out_n(0);
process(clk_i)
begin
......
......@@ -40,7 +40,7 @@ files = [
modules = {"local": ["mpm", "Switched-Multiported-RAM"]}
if (action == "simulation"):
files.append("ram_bug/buggy_ram_synth.vhd")
else:
files.append("ram_bug/buggy_ram.ngc")
#if (action == "simulation"):
# files.append("ram_bug/buggy_ram_synth.vhd")
#else:
# files.append("ram_bug/buggy_ram.ngc")
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-03-18
-- Last update: 2012-03-18
-- Last update: 2020-07-29
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -176,19 +176,36 @@ begin -- rtl
--rd_o <= rd_data(g_data_width-1 downto 0);-- when collided = '0' else wr_data_reg(g_data_width-1 downto 0);
wr_data <= f_slv_resize(wd_i, 32);
rd_addr <= f_slv_resize(ra_i, 10);
wr_addr <= f_slv_resize(wa_i, 10);
U_Buggy_RAM: buggy_ram
wr_addr <=f_slv_resize(wa_i, 10);
generic_simple_dpram_1: generic_simple_dpram
generic map (
g_data_width => 32,
g_size => 1024,
g_with_byte_enable => false,
g_dual_clock => false)
port map (
clka => clk_i,
wea(0) => (we_i),
addra => wr_addr,
dina => wr_data,
clkb => clk_i,
web => "0",
addrb => rd_addr,
dinb => x"00000000",
doutb => rd_data);
rst_n_i => rst_n_i,
clka_i => clk_i,
wea_i => we_i,
aa_i => wr_addr,
da_i => wr_data,
clkb_i => clk_i,
ab_i => rd_addr,
qb_o => rd_data);
-- U_Buggy_RAM: generic_dpram_singleclock
-- port map (
-- clka => clk_i,
-- wea(0) => (we_i),
-- addra => wr_addr,
-- dina => wr_data,
-- clkb => clk_i,
-- web => "0",
-- addrb => rd_addr,
-- dinb => x"00000000",
-- doutb => rd_data);
p_ram : process(clk_i)
......
sim_tool = "modelsim"
top_module = "main"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
modelsim_ini_path="~/eda/modelsim-lib-2016.4"
#modelsim_ini_path="~/eda/modelsim-lib"
vcom_opt="-mixedsvvh l -2008"
vlog_opt=""
syn_device = "xczu17"
include_dirs = ["../../sim", "../include",
"../../ip_cores/wr-cores/sim",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src",
"../../ip_cores/general-cores/modules/wishbone/wb_spi",
"../../modules/wrsw_swcore/Switched-Multiported-RAM/" ]
files = ["main.sv", "glbl.v" ]
modules = { "local": ["../../top/zynq_us/scb_8ports"] }
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.15 2011/08/25 22:54:30 fphillip Exp $
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`timescale 1ps/1ps
`include "simdrv_defs.svh"
`include "axi4_lite_master.sv"
module dupa;
glbl dummy();
afcz_wrs_8p_top dummy2();
endmodule // dupa
class IBusDevice;
CBusAccessor m_acc;
uint64_t m_base;
function new ( CBusAccessor acc, uint64_t base );
m_acc =acc;
m_base = base;
endfunction // new
virtual task write32( uint32_t addr, uint32_t val );
m_acc.write(m_base +addr, val);
endtask // write
virtual task read32( uint32_t addr, output uint32_t val );
uint64_t val64;
m_acc.read(m_base +addr, val64);
val = val64;
endtask // write
endclass // BusDevice
module main;
reg rst_n = 0;
reg clk_startup_62m5 = 0;
reg clk_gth = 0;
reg clk_20m = 0;
always #8ns clk_startup_62m5 <= ~clk_startup_62m5;
always #4ns clk_gth <= ~clk_gth;
always #25ns clk_20m <= ~clk_20m;
initial begin
repeat(30) @(posedge clk_startup_62m5);
rst_n = 1;
end
wire axi4l_aclk;
wire axi4l_aresetn;
IAXI4LiteMaster master ( axi4l_aclk, axi4l_aresetn );
afcz_wrs_8p_top
#(
.g_simulation(1)
)
DUT
(
.sys_rst_n_i(rst_n),
.clk_20m_vcxo_i( clk_20m ),
.clk_startup_i( clk_startup_62m5 ),
.mgtclk1_224_p_i(1'b0), //clk_gth),
.mgtclk1_224_n_i(1'b1), //~clk_gth),
.axi4l_aclk ( axi4l_aclk ),
.axi4l_aresetn ( axi4l_aresetn ),
.axi4l_arvalid ( master.arvalid ),
.axi4l_awvalid ( master.awvalid ),
.axi4l_bready ( master.bready ),
.axi4l_rready ( master.rready),
.axi4l_wlast ( master.wlast ),
.axi4l_wvalid ( master.wvalid ),
.axi4l_araddr ( master.araddr ),
.axi4l_awaddr ( master.awaddr ),
.axi4l_wdata ( master.wdata ),
.axi4l_wstrb ( master.wstrb ),
.axi4l_arready ( master.arready ),
.axi4l_awready ( master.awready ),
.axi4l_bvalid ( master.bvalid ),
.axi4l_rlast ( master.rlast ),
.axi4l_rvalid ( master.rvalid ),
.axi4l_wready ( master.wready ),
.axi4l_bresp ( master.bresp ),
.axi4l_rresp ( master.rresp ),
.axi4l_rdata ( master.rdata )
);
const uint64_t base_endpoints = 'h30000;
initial begin
uint64_t rv;
automatic CBusAccessor acc = master.get_accessor();
int i;
#10us;
$error("WR!");
for(i=0; i<100; i+=1)
acc.write(i*4, i);
acc.read(0, rv); // read idcode from EP0
$display("Rd(0) %x", rv);
acc.read(base_endpoints + 'h34, rv); // read idcode from EP0
$display("IDCode(0) %x", rv);
#100ns;
$stop;
end
endmodule // main
## vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include +incdir+../include +incdir+../../sim
vsim -modelsimini /home/twl/eda/modelsim-lib-2016.4/modelsim.ini -t 1ps work.main work.glbl -L unisim -L secureip -voptargs=+acc
#vsim -modelsimini /home/twl/eda/modelsim-lib/modelsim.ini -t 1ps work.main work.glbl -L unisim -L secureip -voptargs=+acc
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 100us
\ No newline at end of file
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......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2014-09-16
-- Last update: 2014-09-16
-- Last update: 2020-07-28
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -236,8 +236,26 @@ package wrs_sdb_pkg is
date => x"20160810",
name => "WRSW SWCORE ")));
constant c_xwr_si57x_interface_sdb: t_sdb_device := (
abi_class => x"0000",
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7",
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"12345567", -- echo -n "xswc_core" | md5sum - | cut -c1-8
version => x"00000001",
date => x"20160810",
name => "WR-si57x-interface ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(8 downto 0) :=
constant c_rtbar_layout : t_sdb_record_array(9 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
......@@ -246,9 +264,12 @@ package wrs_sdb_pkg is
5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700")); --SPI ext
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700"), --SPI ext
9 => f_sdb_embed_device(c_xwr_si57x_interface_sdb, x"00010800") -- si57x
);
constant c_rtbar_sdb_address : t_wishbone_address := x"00010800";
constant c_rtbar_sdb_address : t_wishbone_address := x"00011000";
constant c_rtbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address);
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-02-14
-- Last update: 2020-07-28
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -205,69 +205,6 @@ package wrsw_components_pkg is
end component;
component wrsw_rt_subsystem
generic (
g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
rst_periph_ref_n_i : in std_logic;
rst_n_o : out std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
dac_helper_data_o : out std_logic;
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
pps_p_o : out std_logic;
pps_raw_i : in std_logic;
sel_clk_sys_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
ext_board_osc_freq_i: in std_logic_vector (2 downto 0);
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic);
end component;
component chipscope_icon
port (
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2018-11-07
-- Last update: 2020-07-28
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -57,6 +57,7 @@ package wrsw_top_pkg is
type t_phyif_input is record
ref_clk : std_logic;
tx_out_clk : std_logic;
tx_disparity : std_logic;
tx_enc_err : std_logic;
rx_data : std_logic_vector(15 downto 0);
......
files = [ "afcz_wrs_8p_top.vhd" ];
modules = { "local" : [ "../../../", "../../bare_top",
"../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/gthe4"
] };
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