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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
Commits
63a4e161
Commit
63a4e161
authored
Jul 16, 2021
by
Tomasz Wlostowski
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afcz wip
parent
59004e8e
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6 changed files
with
156 additions
and
77 deletions
+156
-77
wrsw_rt_subsystem.vhd
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+19
-3
main.sv
testbench/zynq_top/main.sv
+8
-0
wave.do
testbench/zynq_top/wave.do
+72
-10
scb_top_bare.vhd
top/bare_top/scb_top_bare.vhd
+16
-2
afcz_wrs_8p_top.vhd
top/zynq_us/scb_8ports/afcz_wrs_8p_top.vhd
+13
-3
timing.xdc
top/zynq_us/scb_8ports/timing.xdc
+28
-59
No files found.
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @
63a4e161
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2020-0
7-31
-- Last update: 2020-0
8-18
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -154,6 +154,13 @@ entity wrsw_rt_subsystem is
si57x_scl_i
:
in
std_logic
;
si57x_sda_i
:
in
std_logic
;
aux_scl_oen_o
:
out
std_logic
;
aux_sda_oen_o
:
out
std_logic
;
aux_scl_o
:
out
std_logic
;
aux_sda_o
:
out
std_logic
;
aux_scl_i
:
in
std_logic
;
aux_sda_i
:
in
std_logic
;
-- Debug
spll_dbg_o
:
out
std_logic_vector
(
5
downto
0
)
);
...
...
@@ -218,7 +225,7 @@ architecture rtl of wrsw_rt_subsystem is
signal
cpu_reset_n
:
std_logic
;
signal
dummy
:
std_logic_vector
(
63
downto
0
);
signal
gpio_out
,
gpio_in
:
std_logic_vector
(
c_NUM_GPIO_PINS
-1
downto
0
);
signal
gpio_o
en
,
gpio_o
ut
,
gpio_in
:
std_logic_vector
(
c_NUM_GPIO_PINS
-1
downto
0
);
signal
dac_out_data
,
dac_dmtd_data
:
std_logic_vector
(
15
downto
0
);
signal
dac_out_load
,
dac_dmtd_load
:
std_logic
;
...
...
@@ -457,7 +464,7 @@ begin -- rtl
gpio_b
=>
open
,
gpio_out_o
=>
gpio_out
,
gpio_in_i
=>
gpio_in
,
gpio_oen_o
=>
op
en
);
gpio_oen_o
=>
gpio_o
en
);
U_Timer
:
xwb_tics
generic
map
(
...
...
@@ -493,10 +500,19 @@ begin -- rtl
pll_reset_n_o
<=
gpio_out
(
1
);
cpu_reset_n
<=
not
gpio_out
(
2
)
and
rst_sys_n_i
;
rst_n_o
<=
gpio_out
(
3
);
gpio_in
(
4
)
<=
ljd_board_detected
;
gpio_in
(
7
downto
5
)
<=
ljd_osc_freq_i
;
aux_scl_oen_o
<=
gpio_oen
(
8
);
aux_sda_oen_o
<=
gpio_oen
(
9
);
aux_scl_o
<=
'0'
;
aux_sda_o
<=
'0'
;
gpio_in
(
8
)
<=
aux_scl_i
;
gpio_in
(
9
)
<=
aux_sda_i
;
dac_main_value_o
<=
dac_out_data
;
dac_main_load_o
<=
dac_out_load
;
...
...
testbench/zynq_top/main.sv
View file @
63a4e161
...
...
@@ -103,6 +103,14 @@ module main;
$
error
(
"WR!"
)
;
acc
.
write
(
'h10304
,
'h8
)
;
acc
.
write
(
'h54000
,
'haa
)
;
acc
.
read
(
'h54000
,
rv
)
;
$
display
(
"Rd(0) %x"
,
rv
)
;
$
stop
;
for
(
i
=
0
;
i
<
100
;
i
+=
1
)
acc
.
write
(
i
*
4
,
i
)
;
...
...
testbench/zynq_top/wave.do
View file @
63a4e161
...
...
@@ -451,16 +451,78 @@ add wave -noupdate -group Ep0WB /main/DUT/U_Real_Top/gen_network_stuff/gen_endpo
add wave -noupdate -group Ep0WB /main/DUT/U_Real_Top/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/rd_int
add wave -noupdate -group Ep0WB /main/DUT/U_Real_Top/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/allones
add wave -noupdate -group Ep0WB /main/DUT/U_Real_Top/gen_network_stuff/gen_endpoints_and_phys(0)/U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/allzeros
add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/clk_sys_i
add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/rst_n_i
add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/axi4_slave_i
add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/axi4_slave_o
add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/wb_master_o
add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/wb_master_i
add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/state
add wave -noupdate -expand -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/count
add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/clk_sys_i
add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/rst_n_i
add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/axi4_slave_i
add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/axi4_slave_o
add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/wb_master_o
add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/wb_master_i
add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/state
add wave -noupdate -group Brg /main/DUT/U_axi4lite_bridge/U_Wrapped_Bridge/count
add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/clk_sys_i
add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/rst_n_i
add wave -noupdate -group i2c -expand /main/DUT/U_Real_Top/U_MiniBackplane_I2C/slave_i
add wave -noupdate -group i2c -expand /main/DUT/U_Real_Top/U_MiniBackplane_I2C/slave_o
add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/desc_o
add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/int_o
add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/scl_pad_i
add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/scl_pad_o
add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/scl_padoen_o
add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/sda_pad_i
add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/sda_pad_o
add wave -noupdate -group i2c /main/DUT/U_Real_Top/U_MiniBackplane_I2C/sda_padoen_o
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_clk_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_rst_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/arst_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_adr_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_we_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_stb_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_cyc_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_ack_o
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/inta_o
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_pad_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_pad_o
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_padoen_o
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_pad_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_pad_o
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_padoen_o
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/prer
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/txr
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/rxr
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/cr
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sr
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/rst_i
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_wacc
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/iack_o
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/done
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sta
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sto
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/rd
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wr
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ack
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/iack
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/core_en
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ien
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/irxack
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/rxack
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/tip
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/irq_flag
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/i2c_busy
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/al
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/i2c_al
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_in
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_out
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/scl_oen
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_in
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_out
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/sda_oen
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/if_num
add wave -noupdate -expand -group I2CM /main/DUT/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/if_busy
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1
2478773
ps} 0}
WaveRestoreCursors {{Cursor 1} {1
0721600
ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
...
...
@@ -475,4 +537,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {
0 ps} {32768 n
s}
WaveRestoreZoom {
8673600 ps} {12769600 p
s}
top/bare_top/scb_top_bare.vhd
View file @
63a4e161
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2020-0
7-31
-- Last update: 2020-0
8-18
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -196,7 +196,14 @@ entity scb_top_bare is
rts_si57x_sda_oen_o
:
out
std_logic
;
rts_si57x_scl_i
:
in
std_logic
;
rts_si57x_sda_i
:
in
std_logic
;
aux_scl_oen_o
:
out
std_logic
;
aux_sda_oen_o
:
out
std_logic
;
aux_scl_o
:
out
std_logic
;
aux_sda_o
:
out
std_logic
;
aux_scl_i
:
in
std_logic
;
aux_sda_i
:
in
std_logic
;
---------------------------------------------------------------------------
-- Mini-backplane PWM fans
---------------------------------------------------------------------------
...
...
@@ -659,6 +666,13 @@ begin
si57x_sda_oen_o
=>
rts_si57x_sda_oen_o
,
si57x_scl_i
=>
rts_si57x_scl_i
,
si57x_sda_i
=>
rts_si57x_sda_i
,
aux_scl_i
=>
aux_scl_i
,
aux_sda_i
=>
aux_sda_i
,
aux_scl_o
=>
aux_scl_o
,
aux_sda_o
=>
aux_sda_o
,
aux_scl_oen_o
=>
aux_scl_oen_o
,
aux_sda_oen_o
=>
aux_sda_oen_o
,
spll_dbg_o
=>
spll_dbg_o
);
...
...
top/zynq_us/scb_8ports/afcz_wrs_8p_top.vhd
View file @
63a4e161
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-03-07
-- Last update: 2020-08-
09
-- Last update: 2020-08-
18
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -270,6 +270,8 @@ architecture Behavioral of afcz_wrs_8p_top is
signal
mgtclk1_224
,
mgtclk1_224_prebuf
:
std_logic
;
signal
aux_scl_oen
,
aux_sda_oen
:
std_logic
;
signal
afcz_scl_oen
,
afcz_sda_oen
:
std_logic
;
begin
...
...
@@ -595,6 +597,11 @@ begin
rts_si57x_scl_i
=>
rts_si57x_scl_in
,
rts_si57x_sda_i
=>
rts_si57x_sda_in
,
aux_scl_i
=>
i2c_scl_in
(
0
),
aux_sda_i
=>
i2c_sda_in
(
0
),
aux_scl_oen_o
=>
aux_scl_oen
,
aux_sda_oen_o
=>
aux_sda_oen
,
rts_gpio_o
=>
rts_gpio_out
,
rts_gpio_i
=>
rts_gpio_in
...
...
@@ -626,19 +633,22 @@ begin
T
=>
rts_si57x_scl_oen
);
afcz_scl_oen
<=
i2c_scl_oen
(
0
)
and
aux_scl_oen
;
afcz_sda_oen
<=
i2c_sda_oen
(
0
)
and
aux_sda_oen
;
IOBUF_3
:
IOBUF
port
map
(
O
=>
i2c_scl_in
(
0
),
IO
=>
afcz_scl_b
,
I
=>
i2c_scl_out
(
0
),
T
=>
i2c_scl_oen
(
0
)
);
T
=>
afcz_scl_oen
);
IOBUF_4
:
IOBUF
port
map
(
O
=>
i2c_sda_in
(
0
),
IO
=>
afcz_sda_b
,
I
=>
i2c_sda_out
(
0
),
T
=>
i2c_sda_oen
(
0
)
);
T
=>
afcz_sda_oen
);
U_WR_DACs
:
entity
work
.
spec_serial_dac_arb
...
...
top/zynq_us/scb_8ports/timing.xdc
View file @
63a4e161
...
...
@@ -30,6 +30,7 @@ create_clock -period 16.000 -name clk_rx6 -waveform {0.000 8.000} [get_nets {top
create_clock -period 16.000 -name clk_rx7 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[7].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
create_generated_clock -name clk_dmtd_62_5 -source [get_pins top_i/afcz_wrs_8p_top_0/inst/U_DMTD_Clock_PLL/CLKIN1] -master_clock clk_20m_vcxo1_i [get_pins top_i/afcz_wrs_8p_top_0/inst/U_DMTD_Clock_PLL/CLKOUT0]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
...
...
@@ -42,108 +43,76 @@ set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list top_i/cmp_zynq/inst/pl_clk0]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width
32
[get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/
host_master_in[dat][0]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][1]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][2]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][3]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][4]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][5]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][6]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][7]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][8]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][9]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][10]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][11]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][12]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][13]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][14]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][15]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][16]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][17]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][18]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][19]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][20]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][21]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][22]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][23]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][24]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][25]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][26]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][27]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][28]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][29]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][30]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][31
]}]]
set_property port_width
8
[get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/
U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[0]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[1]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[2]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[3]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[4]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[5]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[6]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_dat_i[7
]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 3
2
[get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/
host_master_out[dat][0]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][1]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][2]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][3]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][4]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][5]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][6]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][7]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][8]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][9]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][10]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][11]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][12]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][13]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][14]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][15]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][16]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][17]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][18]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][19]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][20]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][21]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][22]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][23]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][24]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][25]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][26]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][27]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][28]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][29]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][30]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][31
]}]]
set_property port_width 3 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/
U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_adr_i[0]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_adr_i[1]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_adr_i[2
]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width
32
[get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/
host_master_out[adr][0]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][1]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][2]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][3]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][4]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][5]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][6]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][7]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][8]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][9]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][10]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][11]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][12]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][13]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][14]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][15]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][16]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][17]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][18]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][19]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][20]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][21]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][22]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][23]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][24]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][25]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][26]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][27]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][28]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][29]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][30]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][31
]}]]
set_property port_width
8
[get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/
U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[0]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[1]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[2]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[3]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[4]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[5]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[6]} {top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/ctr[7
]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width
1
[get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[
sel][0
]}]]
set_property port_width
32
[get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[
adr][0]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][1]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][2]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][3]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][4]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][5]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][6]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][7]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][8]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][9]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][10]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][11]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][12]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][13]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][14]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][15]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][16]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][17]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][18]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][19]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][20]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][21]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][22]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][23]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][24]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][25]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][26]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][27]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][28]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][29]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][30]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[adr][31
]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width
17
[get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {top_i/afcz_wrs_8p_top_0/
axi4l_awaddr[2]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[3]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[4]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[5]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[6]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[7]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[8]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[9]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[10]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[11]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[12]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[13]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[14]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[15]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[16]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[17]} {top_i/afcz_wrs_8p_top_0/axi4l_awaddr[18
]}]]
set_property port_width
32
[get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {top_i/afcz_wrs_8p_top_0/
inst/host_master_in[dat][0]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][1]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][2]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][3]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][4]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][5]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][6]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][7]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][8]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][9]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][10]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][11]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][12]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][13]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][14]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][15]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][16]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][17]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][18]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][19]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][20]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][21]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][22]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][23]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][24]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][25]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][26]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][27]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][28]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][29]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][30]} {top_i/afcz_wrs_8p_top_0/inst/host_master_in[dat][31
]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 32 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {top_i/afcz_wrs_8p_top_0/
axi4l_rdata[0]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[1]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[2]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[3]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[4]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[5]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[6]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[7]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[8]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[9]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[10]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[11]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[12]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[13]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[14]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[15]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[16]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[17]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[18]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[19]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[20]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[21]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[22]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[23]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[24]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[25]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[26]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[27]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[28]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[29]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata[30]} {top_i/afcz_wrs_8p_top_0/axi4l_rdata
[31]}]]
connect_debug_port u_ila_0/probe5 [get_nets [list {top_i/afcz_wrs_8p_top_0/
inst/host_master_out[dat][0]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][1]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][2]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][3]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][4]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][5]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][6]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][7]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][8]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][9]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][10]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][11]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][12]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][13]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][14]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][15]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][16]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][17]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][18]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][19]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][20]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][21]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][22]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][23]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][24]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][25]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][26]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][27]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][28]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][29]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat][30]} {top_i/afcz_wrs_8p_top_0/inst/host_master_out[dat]
[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width
2
[get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {top_i/afcz_wrs_8p_top_0/
axi4l_bresp[0]} {top_i/afcz_wrs_8p_top_0/axi4l_bresp[1
]}]]
set_property port_width
1
[get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {top_i/afcz_wrs_8p_top_0/
inst/host_master_out[sel][0
]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width
2
[get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {top_i/afcz_wrs_8p_top_0/
axi4l_rresp[0]} {top_i/afcz_wrs_8p_top_0/axi4l_rresp[1
]}]]
set_property port_width
1
[get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {top_i/afcz_wrs_8p_top_0/
inst/host_master_in[ack
]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width
32
[get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {top_i/afcz_wrs_8p_top_0/
axi4l_wdata[0]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[1]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[2]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[3]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[4]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[5]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[6]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[7]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[8]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[9]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[10]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[11]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[12]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[13]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[14]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[15]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[16]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[17]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[18]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[19]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[20]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[21]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[22]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[23]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[24]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[25]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[26]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[27]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[28]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[29]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[30]} {top_i/afcz_wrs_8p_top_0/axi4l_wdata[31
]}]]
set_property port_width
1
[get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {top_i/afcz_wrs_8p_top_0/
inst/host_master_in[err
]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1
7
[get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {top_i/afcz_wrs_8p_top_0/
axi4l_araddr[2]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[3]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[4]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[5]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[6]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[7]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[8]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[9]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[10]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[11]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[12]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[13]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[14]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[15]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[16]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[17]} {top_i/afcz_wrs_8p_top_0/axi4l_araddr[18
]}]]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {top_i/afcz_wrs_8p_top_0/
inst/host_master_in[stall
]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list
top_i/afcz_wrs_8p_top_0/axi4l_arready
]]
connect_debug_port u_ila_0/probe10 [get_nets [list
{top_i/afcz_wrs_8p_top_0/inst/host_master_out[cyc]}
]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list
top_i/afcz_wrs_8p_top_0/axi4l_arvalid
]]
connect_debug_port u_ila_0/probe11 [get_nets [list
{top_i/afcz_wrs_8p_top_0/inst/host_master_out[stb]}
]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list
top_i/afcz_wrs_8p_top_0/axi4l_awvalid
]]
connect_debug_port u_ila_0/probe12 [get_nets [list
{top_i/afcz_wrs_8p_top_0/inst/host_master_out[we]}
]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list top_i/afcz_wrs_8p_top_0/
axi4l_bready
]]
connect_debug_port u_ila_0/probe13 [get_nets [list top_i/afcz_wrs_8p_top_0/
inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_ack_o
]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list top_i/afcz_wrs_8p_top_0/
axi4l_bvalid
]]
connect_debug_port u_ila_0/probe14 [get_nets [list top_i/afcz_wrs_8p_top_0/
inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_cyc_i
]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list top_i/afcz_wrs_8p_top_0/
axi4l_rlast
]]
connect_debug_port u_ila_0/probe15 [get_nets [list top_i/afcz_wrs_8p_top_0/
inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_rst_i
]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list top_i/afcz_wrs_8p_top_0/
axi4l_rready
]]
connect_debug_port u_ila_0/probe16 [get_nets [list top_i/afcz_wrs_8p_top_0/
inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_stb_i
]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list top_i/afcz_wrs_8p_top_0/axi4l_rvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list top_i/afcz_wrs_8p_top_0/axi4l_wready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list top_i/afcz_wrs_8p_top_0/axi4l_wvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_in[ack]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_in[err]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_in[stall]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[cyc]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[stb]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list {top_i/afcz_wrs_8p_top_0/inst/host_master_out[we]}]]
connect_debug_port u_ila_0/probe17 [get_nets [list top_i/afcz_wrs_8p_top_0/inst/U_Real_Top/U_MiniBackplane_I2C/U_Wrapped_I2C/Wrapped_I2C/wb_we_i]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
...
...
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