swcore[generic-azing]: no more global constants !!! -> fully generic-azed,...

swcore[generic-azing]: no more global constants !!! -> fully generic-azed, removed global constants from the swc_swcore_pkg.vhd (not tested yet for different generic values, there is a known problem inherited from global consants - does not work when some configs are changed

modules/wrsw_swcore/Manifest.py

@@ -11,13 +11,13 @@ files = [
 "swc_swcore_pkg.vhd",
 "swc_block_alloc.vhd",
 "swc_core.vhd",
-"swc_input_block.vhd",
+#"swc_input_block.vhd",
 #"swc_lost_pck_dealloc.vhd",
 "swc_multiport_linked_list.vhd",
 "swc_multiport_page_allocator.vhd",
 "swc_multiport_pck_pg_free_module.vhd",
 "swc_ob_prio_queue.vhd",
-"swc_output_block.vhd",
+#"swc_output_block.vhd",
 "swc_packet_mem.vhd",
 "swc_packet_mem_read_pump.vhd",
 "swc_packet_mem_write_pump.vhd",

modules/wrsw_swcore/swc_core.vhd

@@ -57,7 +57,7 @@ entity swc_core is
     g_mem_size                         : integer ;--:= c_swc_packet_mem_size
     g_page_size                        : integer ;--:= c_swc_page_size
     g_prio_num                         : integer ;--:= c_swc_output_prio_num;
-    g_max_pck_size_width               : integer ;--:= c_swc_max_pck_size_width    
+    g_max_pck_size                     : integer ;--:= c_swc_max_pck_size
     g_num_ports                        : integer ;--:= c_swc_num_ports
     g_data_width                       : integer ;--:= c_swc_data_width
     g_ctrl_width                       : integer ; --:= c_swc_ctrl_width
@@ -105,6 +105,7 @@ architecture rtl of swc_core is
 
    constant c_page_num              : integer := (g_mem_size / g_page_size); -- 65536/64 = 1024 -- c_swc_packet_mem_num_pages
    constant c_page_addr_width       : integer := integer(CEIL(LOG2(real(c_page_num-1)))); --c_swc_page_addr_width
+   constant c_max_pck_size_width    : integer := integer(CEIL(LOG2(real(g_max_pck_size-1)))); -- c_swc_max_pck_size_width 
    ----------------------------------------------------------------------------------------------------
    -- signals connecting >>Input Block<< with >>Memory Management Unit<<
    ----------------------------------------------------------------------------------------------------
@@ -145,7 +146,7 @@ architecture rtl of swc_core is
    signal ib_pageaddr_to_pta  : std_logic_vector(g_num_ports * c_page_addr_width - 1 downto 0);
    signal ib_mask             : std_logic_vector(g_num_ports * g_num_ports - 1 downto 0);
    signal ib_prio             : std_logic_vector(g_num_ports * c_prio_width - 1 downto 0);
-   signal ib_pck_size         : std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0);
+   signal ib_pck_size         : std_logic_vector(g_num_ports * c_max_pck_size_width - 1 downto 0);
    
    -- Pck Transfer Arbiter -> Input Block       
    signal pta_transfer_ack    : std_logic_vector(g_num_ports - 1 downto 0);  
@@ -158,7 +159,7 @@ architecture rtl of swc_core is
    signal pta_data_valid             : std_logic_vector(g_num_ports -1 downto 0);
    signal pta_pageaddr               : std_logic_vector(g_num_ports * c_page_addr_width    - 1 downto 0);
    signal pta_prio                   : std_logic_vector(g_num_ports * c_prio_width         - 1 downto 0);
-   signal pta_pck_size               : std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0);
+   signal pta_pck_size               : std_logic_vector(g_num_ports * c_max_pck_size_width - 1 downto 0);
 
    -- Input Block -> Pck Transfer Arbiter
    signal ob_ack                    : std_logic_vector(g_num_ports -1 downto 0);
@@ -258,7 +259,7 @@ architecture rtl of swc_core is
         g_page_addr_width                  => c_page_addr_width,
         g_num_ports                        => g_num_ports,
         g_prio_width                       => c_prio_width,
-        g_max_pck_size_width               => g_max_pck_size_width,
+        g_max_pck_size_width               => c_max_pck_size_width,
         g_usecount_width                   => c_usecount_width,
         g_data_width                       => g_data_width,
         g_ctrl_width                       => g_ctrl_width,
@@ -327,7 +328,7 @@ architecture rtl of swc_core is
         pta_pageaddr_o           => ib_pageaddr_to_pta((i + 1) * c_page_addr_width    -1 downto i * c_page_addr_width),
         pta_mask_o               => ib_mask           ((i + 1) * g_num_ports          -1 downto i * g_num_ports),
         pta_prio_o               => ib_prio           ((i + 1) * c_prio_width         -1 downto i * c_prio_width),
-        pta_pck_size_o           => ib_pck_size       ((i + 1) * g_max_pck_size_width -1 downto i * g_max_pck_size_width)
+        pta_pck_size_o           => ib_pck_size       ((i + 1) * c_max_pck_size_width -1 downto i * c_max_pck_size_width)
        
         );
         
@@ -336,7 +337,7 @@ architecture rtl of swc_core is
     OUTPUT_BLOCK: xswc_output_block
       generic map( 
         g_page_addr_width                  => c_page_addr_width,
-        g_max_pck_size_width               => g_max_pck_size_width,
+        g_max_pck_size_width               => c_max_pck_size_width,
         g_data_width                       => g_data_width,
         g_ctrl_width                       => g_ctrl_width,
         g_output_block_per_prio_fifo_size  => g_output_block_per_prio_fifo_size,
@@ -352,7 +353,7 @@ architecture rtl of swc_core is
         pta_transfer_data_valid_i=> pta_data_valid(i),
         pta_pageaddr_i           => pta_pageaddr((i + 1) * c_page_addr_width    -1 downto i * c_page_addr_width),
         pta_prio_i               => pta_prio    ((i + 1) * c_prio_width         -1 downto i * c_prio_width),
-        pta_pck_size_i           => pta_pck_size((i + 1) * g_max_pck_size_width -1 downto i * g_max_pck_size_width),
+        pta_pck_size_i           => pta_pck_size((i + 1) * c_max_pck_size_width -1 downto i * c_max_pck_size_width),
         pta_transfer_data_ack_o  => ob_ack(i),
         -------------------------------------------------------------------------------
         -- I/F with Multiport Memory (MPM)
@@ -491,6 +492,16 @@ architecture rtl of swc_core is
   -- MultiPort Memory (MPM) [ 1 module]
   ----------------------------------------------------------------------
   MUPTIPORT_MEMORY: swc_packet_mem
+    generic map( 
+      g_mem_size                 => g_mem_size,
+      g_num_ports                => g_num_ports,
+      g_page_num                 => c_page_num,
+      g_page_addr_width          => c_page_addr_width,
+      g_data_width               => g_data_width,
+      g_ctrl_width               => g_ctrl_width,
+      g_page_size                => g_page_size,
+      g_packet_mem_multiply      => g_packet_mem_multiply
+      )
     port map(
       clk_i                      => clk_i,
       rst_n_i                    => rst_n_i,
@@ -545,7 +556,7 @@ architecture rtl of swc_core is
     generic map(
       g_page_addr_width    => c_page_addr_width,
       g_prio_width         => c_prio_width,    
-      g_max_pck_size_width => g_max_pck_size_width,
+      g_max_pck_size_width => c_max_pck_size_width,
       g_num_ports          => g_num_ports
       )
     port map(

modules/wrsw_swcore/swc_multiport_page_allocator.vhd

@@ -168,6 +168,7 @@ begin  -- syn
     generic map (
       g_num_pages      => g_page_num,
       g_page_addr_width=> g_page_addr_width,
+      g_num_ports      => g_page_num,
       g_usecount_width => g_usecount_width)
     port map (
       clk_i          => clk_i,

modules/wrsw_swcore/swc_ob_prio_queue.vhd

@@ -6,7 +6,7 @@
 -- Author     : Maciej Lipinski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-11-03
--- Last update: 2010-11-03
+-- Last update: 2012-02-02
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'87
 -------------------------------------------------------------------------------
@@ -35,7 +35,7 @@
 -- Revisions  :
 -- Date        Version  Author   Description
 -- 2010-11-09  1.0      mlipinsk created
-
+-- 2012-02-02  2.0      mlipinsk generic-azed
 -------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
@@ -47,7 +47,9 @@ use work.swc_swcore_pkg.all;
 
 
 entity swc_ob_prio_queue is
-
+  generic(
+    g_per_prio_fifo_size_width : integer --:= c_swc_output_fifo_addr_width
+    );
   port (
     clk_i   : in std_logic;
     rst_n_i : in std_logic;
@@ -67,8 +69,8 @@ entity swc_ob_prio_queue is
 -------------------------------------------------------------------------------
     
     wr_en_o           : out  std_logic;
-    wr_addr_o         : out  std_logic_vector(c_swc_output_fifo_addr_width - 1 downto 0);
-    rd_addr_o         : out  std_logic_vector(c_swc_output_fifo_addr_width - 1 downto 0)
+    wr_addr_o         : out  std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0);
+    rd_addr_o         : out  std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0)
     
     );
 end swc_ob_prio_queue;
@@ -76,8 +78,8 @@ end swc_ob_prio_queue;
 
 architecture behavoural of swc_ob_prio_queue is
   
-  signal head          : std_logic_vector(c_swc_output_fifo_addr_width - 1  downto 0);
-  signal tail          : std_logic_vector(c_swc_output_fifo_addr_width - 1  downto 0);
+  signal head          : std_logic_vector(g_per_prio_fifo_size_width - 1  downto 0);
+  signal tail          : std_logic_vector(g_per_prio_fifo_size_width - 1  downto 0);
   signal not_full      : std_logic;  
   signal not_empty     : std_logic;
     

modules/wrsw_swcore/swc_output_block.vhd

@@ -273,6 +273,9 @@ begin  --  behavoural
     read(i)         <= read_array(i)  when (state = SET_PAGE) else '0';--rx_dreq_i;
       
     PRIO_QUEUE_CTRL : swc_ob_prio_queue
+      generic map(
+        g_per_prio_fifo_size_width => c_swc_output_fifo_addr_width
+       )
       port map (
         clk_i       => clk_i,
         rst_n_i     => rst_n_i,

modules/wrsw_swcore/swc_packet_mem_read_pump.vhd

@@ -6,11 +6,11 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-04-08
--- Last update: 2010-10-12
+-- Last update: 2012-02-02
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'87
 -------------------------------------------------------------------------------
--- Description: This piece of code reads a bunch ('c_swc_packet_mem_multiply'
+-- Description: This piece of code reads a bunch ('g_packet_mem_multiply'
 -- of words = ctrl + data) from the FUCKING BIG SRAM and makes it available
 -- for read by port. There is one read_pump for each port. Each pump has its
 -- time slot to read from FB SRAM. 
@@ -19,9 +19,9 @@
 -- the thing works in the following way:
 -- 1) it takes the address (FB SRAM addr) of the page
 -- 2) it reads it in its time slot which is one cycle every 
---    c_swc_packet_mem_multiply cycles
+--    g_packet_mem_multiply cycles
 -- 3) it makes it available on its output (d_o) word by word (in number of
---    c_swc_packet_mem_multiply words, this is how many words is saved in 
+--    g_packet_mem_multiply words, this is how many words is saved in 
 --    on FB SRAM word)
 -- 4) it announces it with 'drdy_o' HIGH
 -- 5) the next word is available after setting dreq_i high
@@ -54,6 +54,7 @@
 -- Date        Version  Author   Description
 -- 2010-04-08  1.0      twlostow Created
 -- 2010-10-12  1.1      mlipinsk comments added !!!!!
+-- 2012-02-02  2.0      mlipinsk generic-azed
 -------------------------------------------------------------------------------
 
 
@@ -67,7 +68,15 @@ library work;
 use work.swc_swcore_pkg.all;
 
 entity swc_packet_mem_read_pump is
-
+  generic ( 
+      g_page_addr_width                  : integer ;--:= c_swc_page_addr_width;
+      g_pump_data_width                  : integer ;--:= c_swc_pump_width
+      g_mem_addr_width                   : integer ;--:= c_swc_packet_mem_addr_width
+      g_page_addr_offset_width           : integer ;--:= c_swc_page_offset_width
+
+      -- probably useless with new memory
+      g_packet_mem_multiply              : integer --:= c_swc_packet_mem_multiply
+    );
   port (
     clk_i   : in std_logic;
     rst_n_i : in std_logic;
@@ -77,13 +86,13 @@ entity swc_packet_mem_read_pump is
     pgreq_i  : in  std_logic;
     
     -- Next page address input (from page allocator)
-    pgaddr_i : in  std_logic_vector(c_swc_page_addr_width - 1 downto 0);
+    pgaddr_i : in  std_logic_vector(g_page_addr_width - 1 downto 0);
     
     -- end of package
     pckend_o : out std_logic;
     
     -- HI indicates that current page is done, and that the parent entity must
-    -- select another page in following clock cycles (c_swc_packet_mem_multiply
+    -- select another page in following clock cycles (g_packet_mem_multiply
     -- 2) if it wants to write more data into the memory
     
     -- ML: BUG : it's assigned directly to the output, that sucks, it should be
@@ -105,25 +114,25 @@ entity swc_packet_mem_read_pump is
     sync_read_i : in std_logic;
     
     -- address in LL SRAM which corresponds to the page address
-    --current_page_addr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0);
-    ll_read_addr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0);
+    --current_page_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+    ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
 
     -- data output for LL SRAM - it is the address of the next page or 0xF...F
     -- if this is the last page of the package
-    --next_page_addr_i    : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
-    ll_read_data_i    : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
+    --next_page_addr_i    : in std_logic_vector(g_page_addr_width - 1 downto 0);
+    ll_read_data_i    : in std_logic_vector(g_page_addr_width - 1 downto 0);
     
     ll_read_req_o : out std_logic;
     
     ll_read_valid_data_i : in std_logic;
    
     -- the data we want: one word= ctrl+data
-    d_o    : out std_logic_vector(c_swc_pump_width - 1 downto 0);
+    d_o    : out std_logic_vector(g_pump_data_width - 1 downto 0);
 
     -- strobe indicating the time slot for this pump
     sync_i : in  std_logic;
     
-    -- address in FB SRAM from which the FB SRAM word ( c_swc_packet_mem_multiply 
+    -- address in FB SRAM from which the FB SRAM word ( g_packet_mem_multiply 
     -- of words=ctrl+data) is to be read in the pump's time slot
     --------------
     -- IMPORTANT :
@@ -131,10 +140,10 @@ entity swc_packet_mem_read_pump is
     -- this address output needs to be multiplexed so that it is 'visible' by
     -- FBSRAM during the pump's time slot (sync_i is HIGH). It means that 
     -- the timeslot for reading addr_o by multiplexer is one cycle before sync_i !!!
-    addr_o : out std_logic_vector(c_swc_packet_mem_addr_width - 1 downto 0);
+    addr_o : out std_logic_vector(g_mem_addr_width - 1 downto 0);
     
     -- data read from FB SRAM 
-    q_i    : in  std_logic_vector(c_swc_pump_width * c_swc_packet_mem_multiply -1 downto 0)
+    q_i    : in  std_logic_vector(g_pump_data_width * g_packet_mem_multiply -1 downto 0)
     );
 
 end swc_packet_mem_read_pump;
@@ -143,7 +152,9 @@ end swc_packet_mem_read_pump;
 
 architecture syn of swc_packet_mem_read_pump is
 
-  -- the register to hold c_swc_packet_mem_multiply words(ctrl+data) read from
+  subtype t_pump_entry is std_logic_vector(g_pump_data_width-1 downto 0);
+  type t_pump_reg is array (g_packet_mem_multiply-1 downto 0) of t_pump_entry;
+  -- the register to hold g_packet_mem_multiply words(ctrl+data) read from
   -- one FB SRAM word
   signal out_reg       : t_pump_reg;
   
@@ -161,7 +172,7 @@ architecture syn of swc_packet_mem_read_pump is
   signal cntr_full     : std_logic;
   
   -- address to be suplied to FB SRAM, consists of the pgaddr and page-internal address
-  signal mem_addr      : std_logic_vector (c_swc_packet_mem_addr_width - 1 downto 0);
+  signal mem_addr      : std_logic_vector (g_mem_addr_width - 1 downto 0);
   
   -- ... we love VHDL ...
   signal allones       : std_logic_vector(63 downto 0);
@@ -177,16 +188,16 @@ architecture syn of swc_packet_mem_read_pump is
  -- signal nothing_read : std_logic;
   
   -- HI indicates that current page is done, and that the parent entity must
-  -- select another page in following clock cycles (c_swc_packet_mem_multiply
+  -- select another page in following clock cycles (g_packet_mem_multiply
   -- 2) if it wants to write more data into the memory
   signal pgend        : std_logic;
   
   -- page end
   signal pckend : std_logic;
   
-  signal current_page_addr : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
+  signal current_page_addr : std_logic_vector(g_page_addr_width - 1 downto 0);
 
-  signal next_page_addr    : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
+  signal next_page_addr    : std_logic_vector(g_page_addr_width - 1 downto 0);
   
   signal ll_read_req       : std_logic;
 
@@ -202,7 +213,7 @@ begin  -- syn
   zeros <= (others => '0');
   
   -- last word from out_reg read
-  cntr_full    <= '1' when cntr = to_unsigned(c_swc_packet_mem_multiply-1, cntr'length)                 else '0';
+  cntr_full    <= '1' when cntr = to_unsigned(g_packet_mem_multiply-1, cntr'length)                 else '0';
   
   -- reading new FB SRAM word is needed. it happens in the pump's time slot only if :
   -- * out_reg is empty (used in case there is no request to read data from the pump ????)
@@ -249,8 +260,8 @@ begin  -- syn
 
         if(pgreq_i = '1') then
           -- writing FB SRAM web address which consists of page address and page-internal address
-          mem_addr(c_swc_packet_mem_addr_width-1 downto c_swc_page_offset_width) <= pgaddr_i;
-          mem_addr(c_swc_page_offset_width-1 downto 0)                           <= (others => '0');
+          mem_addr(g_mem_addr_width-1 downto g_page_addr_offset_width) <= pgaddr_i;
+          mem_addr(g_page_addr_offset_width-1 downto 0)                           <= (others => '0');
           pgend                                                                  <= '0';
           current_page_addr <= pgaddr_i;
           pckend            <='0';
@@ -264,25 +275,25 @@ begin  -- syn
           --ll_read_req       <= '1';
         elsif(sync_d1 = '1' and advance_addr = '1' and pgreq_i = '0' and pgreq_d0 = '0') then
           -- incrementing address inside the same page 
-          mem_addr(c_swc_page_offset_width-1 downto 0) <= std_logic_vector(unsigned(mem_addr(c_swc_page_offset_width-1 downto 0)) + 1);
+          mem_addr(g_page_addr_offset_width-1 downto 0) <= std_logic_vector(unsigned(mem_addr(g_page_addr_offset_width-1 downto 0)) + 1);
 
           -- we are approaching the end of current page. Inform the host entity some
           -- cycles in advance.
           advance_addr <= '0';
-          if(mem_addr(c_swc_page_offset_width-1 downto 0) = allones(c_swc_page_offset_width-1 downto 0)) then
+          if(mem_addr(g_page_addr_offset_width-1 downto 0) = allones(g_page_addr_offset_width-1 downto 0)) then
             
-            if(next_page_addr = allones(c_swc_page_addr_width - 1 downto 0)) then
+            if(next_page_addr = allones(g_page_addr_width - 1 downto 0)) then
               pckend <= '1';
               reading_pck <= '0';
             else
-              mem_addr(c_swc_packet_mem_addr_width-1 downto c_swc_page_offset_width) <= next_page_addr;
-              mem_addr(c_swc_page_offset_width-1 downto 0)                           <= (others => '0');
+              mem_addr(g_mem_addr_width-1 downto g_page_addr_offset_width) <= next_page_addr;
+              mem_addr(g_page_addr_offset_width-1 downto 0)                           <= (others => '0');
             end if;
             pgend <= '1';
           end if;
           
-          if(mem_addr(c_swc_page_offset_width-1 downto 0) = zeros(c_swc_page_offset_width-1 downto 0)) then
-            current_page_addr <= mem_addr(c_swc_packet_mem_addr_width-1 downto c_swc_page_offset_width);
+          if(mem_addr(g_page_addr_offset_width-1 downto 0) = zeros(g_page_addr_offset_width-1 downto 0)) then
+            current_page_addr <= mem_addr(g_mem_addr_width-1 downto g_page_addr_offset_width);
             pgend <= '0';
             
             -- start requesting next address
@@ -303,9 +314,9 @@ begin  -- syn
 --          next_page_addr <= next_page_addr_i;
 
 
-          for i in 0 to c_swc_packet_mem_multiply-1 loop
+          for i in 0 to g_packet_mem_multiply-1 loop
             -- reading the word and putting it into out_reg array
-            out_reg (i) <= q_i(c_swc_pump_width * (i+1) - 1 downto c_swc_pump_width * i);
+            out_reg (i) <= q_i(g_pump_data_width * (i+1) - 1 downto g_pump_data_width * i);
           end loop;
 
         -- we read all the words from out_reg, we want more but it's not
@@ -333,10 +344,10 @@ begin  -- syn
           -- we want to provide new word to the outside word
           -- so we shift  right the words in the array
           if(load_out_reg = '0') then
-            for i in 1 to c_swc_packet_mem_multiply-1 loop
+            for i in 1 to g_packet_mem_multiply-1 loop
               out_reg (i-1) <= out_reg(i);
             end loop;
-            out_reg(c_swc_packet_mem_multiply-1) <= (others => 'X');
+            out_reg(g_packet_mem_multiply-1) <= (others => 'X');
           end if;
         end if;
         

modules/wrsw_swcore/swc_packet_mem_write_pump.vhd

@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-04-08
--- Last update: 2012-01-24
+-- Last update: 2012-02-02
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'87
 -------------------------------------------------------------------------------
@@ -21,7 +21,7 @@
 --    - data consits of a word of ctrl + data seq
 --    - one word can be written at one clock cycle, in such case drdy_i is
 --    - constantly HIGH
--- 2) if entire "vector" of data words is collected ('c_swc_packet_mem_multiply'
+-- 2) if entire "vector" of data words is collected ('g_packet_mem_multiply'
 --    number of data words), such a vector is written to SSRAM to one word:
 --    - the dats is written to SRAM memory address = page_addr + offset
 --    - each "memory page" (indicated by page_addr) consists of a few
@@ -31,7 +31,7 @@
 -- 
 -- Each pump has its 'time slot' (one cycle) to read/write from/to 
 -- *FUCKING BIG SRAM (FB SRAM)*.  The access is granted to each pump in sequence: 
--- 1,2,3...(c_swc_packet_mem_multiply - 1). The access is multiplexed
+-- 1,2,3...(g_packet_mem_multiply - 1). The access is multiplexed
 -- between the pumps. 
 --
 -- If we want to write to the FB SRAM vector not fully filled in with data, 
@@ -66,6 +66,7 @@
 -- 2010-10-12  1.1      mlipinsk comments added !!!!!
 -- 2010-10-18  1.2      mlipinsk clearing register
 -- 2010-11-24  1.3      mlipinsk adding main FSM !
+-- 2012-02-02  2.0      mlipinsk generic-azed
 -------------------------------------------------------------------------------
 
 
@@ -82,8 +83,15 @@ use work.swc_swcore_pkg.all;
 --use work.pck_fio.all;
 
 entity swc_packet_mem_write_pump is
-
-  
+  generic ( 
+      g_page_addr_width                  : integer ;--:= c_swc_page_addr_width;
+      g_pump_data_width                  : integer ;--:= c_swc_pump_width
+      g_mem_addr_width                   : integer ;--:= c_swc_packet_mem_addr_width
+      g_page_addr_offset_width           : integer ;--:= c_swc_page_offset_width
+
+      -- probably useless with new memory
+      g_packet_mem_multiply              : integer --:= c_swc_packet_mem_multiply
+    );  
   port (
     clk_i   : in std_logic;
     rst_n_i : in std_logic;
@@ -93,14 +101,14 @@ entity swc_packet_mem_write_pump is
 -------------------------------------------------------------------------------    
     
     -- Next page address input (from page allocator)
-    pgaddr_i : in  std_logic_vector(c_swc_page_addr_width-1 downto 0);
+    pgaddr_i : in  std_logic_vector(g_page_addr_width-1 downto 0);
     
     -- Next page address input strobe (active HI) - loads internal
     -- memory address register with the address of new page
     pgreq_i  : in  std_logic;
 
     -- HI indicates that current page is done, and that the parent entity must
-    -- select another page in following clock cycles (c_swc_packet_mem_multiply
+    -- select another page in following clock cycles (g_packet_mem_multiply
     -- 2) if it wants to write more data into the memory
     pgend_o  : out std_logic;
 
@@ -113,23 +121,23 @@ entity swc_packet_mem_write_pump is
 
     -- data input. data consists of 'c_swc_ctrl_width' of control data and 
     -- 'c_swc_data_width' of data
-    -- sequence (of 'c_swc_packet_mem_multiply' number) of such data is saved 
+    -- sequence (of 'g_packet_mem_multiply' number) of such data is saved 
     -- in one SRAM memory word at the pgaddr_i
-    d_i    : in  std_logic_vector(c_swc_pump_width -1 downto 0);
+    d_i    : in  std_logic_vector(g_pump_data_width -1 downto 0);
 
     -- data input ready strobe (active HI). Clocks in the data. drdy_i cannot 
     -- be asserted when full_o is active.
     drdy_i  : in  std_logic;
     
     -- input register full (active HI). Indicates that the memory input
-    -- register is full ('c_swc_packet_mem_multiply' words have been written)
+    -- register is full ('g_packet_mem_multiply' words have been written)
     -- it will go back to 0 as soon as the memory input reg is synced to the
     -- shared memory. 
     full_o  : out std_logic;
 
     -- Memory input register flush (active HI). Forces a flush of memory input 
     -- register to the shared memory on the next sync pulse even if the number 
-    -- of words clocked into the pump is less than c_swc_packet_mem_multiply.
+    -- of words clocked into the pump is less than g_packet_mem_multiply.
     flush_i : in  std_logic;
 
 -------------------------------------------------------------------------------
@@ -137,11 +145,11 @@ entity swc_packet_mem_write_pump is
 -------------------------------------------------------------------------------
 
     -- address in LL SRAM which corresponds to the page address
-    ll_addr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0);
+    ll_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
 
     -- data output for LL SRAM - it is the address of the next page or 0xF...F
     -- if this is the last page of the package
-    ll_data_o    : out std_logic_vector(c_swc_page_addr_width - 1 downto 0);
+    ll_data_o    : out std_logic_vector(g_page_addr_width - 1 downto 0);
 
     -- request to write to Linked List, should be high until
     -- ll_wr_done_i indicates successfull write
@@ -151,7 +159,7 @@ entity swc_packet_mem_write_pump is
 -------------------------------------------------------------------------------
 -- shared memory (FB SRAM) interface 
 -- The access is multiplexed with other pumps. Each pump has a one-cycle-timeslot
--- to access the FB SRAM every 'c_swc_packet_mem_multiply' cycles.
+-- to access the FB SRAM every 'g_packet_mem_multiply' cycles.
 -------------------------------------------------------------------------------
 
     -- synchronization pulse. HI indicates a time-slot assigned to this write pump.
@@ -161,10 +169,10 @@ entity swc_packet_mem_write_pump is
     sync_i  : in  std_logic;
 
     -- address output for shared memory block
-    addr_o : out std_logic_vector(c_swc_packet_mem_addr_width -1 downto 0);
+    addr_o : out std_logic_vector(g_mem_addr_width -1 downto 0);
 
     -- data output for shared memory block
-    q_o    : out std_logic_vector(c_swc_pump_width * c_swc_packet_mem_multiply - 1 downto 0);
+    q_o    : out std_logic_vector(g_pump_data_width * g_packet_mem_multiply - 1 downto 0);
 
     -- write strobe output for shared memory block (FB SRAM), multiplexed with other pumps
     we_o   : out std_logic
@@ -180,16 +188,18 @@ architecture rtl of swc_packet_mem_write_pump is
   -- word counter (word consists of ctrl + data), counts words in the 'in_reg' register
   signal cntr      : unsigned(3 downto 0);
 
-  -- memory input register organized as an array of (c_swc_packet_mem_multiply) input
+  subtype t_pump_entry is std_logic_vector(g_pump_data_width-1 downto 0);
+  type t_pump_reg is array (g_packet_mem_multiply-1 downto 0) of t_pump_entry;
+  -- memory input register organized as an array of (g_packet_mem_multiply) input
   -- wordsn (ctrl + data).
   signal in_reg    : t_pump_reg;
   
-  -- indicates that in_reg is full, 'c_swc_packet_mem_multiply' words has been written)
+  -- indicates that in_reg is full, 'g_packet_mem_multiply' words has been written)
   signal reg_full  : std_logic;
 
   -- memory register, consists of 'pg_addr' and in-page count (the number of inside
-  -- page FB SRAM words is: (c_swc_page_size / c_swc_packet_mem_multiply)
-  signal mem_addr  : std_logic_vector (c_swc_packet_mem_addr_width - 1 downto 0);
+  -- page FB SRAM words is: (c_swc_page_size / g_packet_mem_multiply)
+  signal mem_addr  : std_logic_vector (g_mem_addr_width - 1 downto 0);
   
   -- FB SRAM write enable (internal). Translate into write request to FB SRAM. 
   -- the access is multiplexed, so the write request has to be issued in this
@@ -211,7 +221,7 @@ architecture rtl of swc_packet_mem_write_pump is
   --signal zeros : std_logic_vector(63 downto 0);  
 
   -- HI indicates that current page is done, and that the parent entity must
-  -- select another page in following clock cycles (c_swc_packet_mem_multiply
+  -- select another page in following clock cycles (g_packet_mem_multiply
   -- 2) if it wants to write more data into the memory
   signal pgend  : std_logic;
   
@@ -223,19 +233,19 @@ architecture rtl of swc_packet_mem_write_pump is
   --=================================================================================
   
   -- address in LL SRAM which corresponds to the page address
-  signal current_page_addr_int : std_logic_vector(c_swc_page_addr_width -1 downto 0);
+  signal current_page_addr_int : std_logic_vector(g_page_addr_width -1 downto 0);
   
   -- stored during FSM cycle (next->eop), this is needed for the last page of the pck
   -- in such case we need to remember it, otherwise we have problems
-  signal current_page_addr_fsm : std_logic_vector(c_swc_page_addr_width -1 downto 0);
+  signal current_page_addr_fsm : std_logic_vector(g_page_addr_width -1 downto 0);
    
-  signal previous_page_addr_int : std_logic_vector(c_swc_page_addr_width -1 downto 0);
+  signal previous_page_addr_int : std_logic_vector(g_page_addr_width -1 downto 0);
 
   -- internal
-  signal ll_write_addr  : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
+  signal ll_write_addr  : std_logic_vector(g_page_addr_width - 1 downto 0);
   
   -- internal
-  signal ll_write_data  : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
+  signal ll_write_data  : std_logic_vector(g_page_addr_width - 1 downto 0);
   
   -- indicatest that the next address shall be writtent to
   -- Linked List SRAM
@@ -272,7 +282,7 @@ architecture rtl of swc_packet_mem_write_pump is
   signal pgreq_or : std_logic;
   signal pckstart_or : std_logic;  
    
-  signal sync_d    : std_logic_vector(c_swc_packet_mem_multiply - 1 downto 0);
+  signal sync_d    : std_logic_vector(g_packet_mem_multiply - 1 downto 0);
 
 --  signal nasty_wait_full : std_logic;
 
@@ -296,7 +306,7 @@ begin  -- rtl
        else
          
          sync_d(0) <= sync_i;
-         for i in 1 to c_swc_packet_mem_multiply-1 loop
+         for i in 1 to g_packet_mem_multiply-1 loop
            sync_d(i) <= sync_d(i - 1);
          end loop; 
          
@@ -305,7 +315,7 @@ begin  -- rtl
      
   end process;
   
---  before_sync <= sync_d(c_swc_packet_mem_multiply - 2);
+--  before_sync <= sync_d(g_packet_mem_multiply - 2);
   
   write_fsm : process(clk_i, rst_n_i)
   begin
@@ -337,7 +347,7 @@ begin  -- rtl
                state_write   <= S_FLUSH;
                reg_full      <= '1';
                 
-             elsif(cntr = to_unsigned(c_swc_packet_mem_multiply - 2,cntr'length) and drdy_i ='1') then
+             elsif(cntr = to_unsigned(g_packet_mem_multiply - 2,cntr'length) and drdy_i ='1') then
 
                state_write   <= S_READ_LAST_DATA_WORD;       
    --            cnt_last_word <= '1';
@@ -359,7 +369,7 @@ begin  -- rtl
 
                -- during the last address of the page, the Linked list is being written, so we need 
                -- to wait for it to finish
-               elsif(mem_addr(c_swc_page_offset_width-1 downto 0) = allones(c_swc_page_offset_width-1 downto 0) and ll_idle = '0' ) then
+               elsif(mem_addr(g_page_addr_offset_width-1 downto 0) = allones(g_page_addr_offset_width-1 downto 0) and ll_idle = '0' ) then
                  
                  state_write   <= S_WAIT_LL_READY;
                  reg_full      <= '1';
@@ -394,7 +404,7 @@ begin  -- rtl
 --                 
             else -- synch_i = '0'
                
---               if(cntr = to_unsigned(c_swc_packet_mem_multiply -1,cntr'length) and drdy_i = '1') then 
+--               if(cntr = to_unsigned(g_packet_mem_multiply -1,cntr'length) and drdy_i = '1') then 
 --               
                  --==== needs test - start ===
                  if (flush_i = '1') then -- when we flush the last word
@@ -422,7 +432,7 @@ begin  -- rtl
              
           when S_NASTY_WAIT =>
              
-            if(drdy_i = '1' and sync_i = '1' and cntr = to_unsigned(c_swc_packet_mem_multiply -1,cntr'length)) then
+            if(drdy_i = '1' and sync_i = '1' and cntr = to_unsigned(g_packet_mem_multiply -1,cntr'length)) then
     
               state_write   <= S_WRITE_DATA;
               we_int        <= '1';
@@ -490,7 +500,7 @@ begin  -- rtl
   
              if(sync_i = '1' and pgend = '0') then
                
-               if(mem_addr(c_swc_page_offset_width-1 downto 0) = allones(c_swc_page_offset_width-1 downto 0) and ll_idle = '0') then
+               if(mem_addr(g_page_addr_offset_width-1 downto 0) = allones(g_page_addr_offset_width-1 downto 0) and ll_idle = '0') then
                  
                  state_write   <= S_WAIT_LL_READY;
                  reg_full      <= '1';
@@ -534,7 +544,7 @@ begin  -- rtl
   
   
   
---  cntr_full <= '1' when cntr = to_unsigned(c_swc_packet_mem_multiply-1, cntr'length) else '0';
+--  cntr_full <= '1' when cntr = to_unsigned(g_packet_mem_multiply-1, cntr'length) else '0';
   
 
   
@@ -549,7 +559,7 @@ begin  -- rtl
         pgend    <= '0';
   --      next_page_loaded <= '0';
         --pckstart <= '0';
-        for i in 0 to c_swc_packet_mem_multiply-1 loop
+        for i in 0 to g_packet_mem_multiply-1 loop
           in_reg(i) <= (others => '0');
         end loop;  -- i 
         
@@ -570,10 +580,10 @@ begin  -- rtl
         
           pgend                <= '0';
           
-        elsif(mem_addr(c_swc_page_offset_width-1 downto 0) = allones(c_swc_page_offset_width-1 downto 0) ) then          
+        elsif(mem_addr(g_page_addr_offset_width-1 downto 0) = allones(g_page_addr_offset_width-1 downto 0) ) then          
           
           
-          if(cntr = to_unsigned(c_swc_packet_mem_multiply -1,cntr'length) and sync_i = '1' and drdy_i = '1') then
+          if(cntr = to_unsigned(g_packet_mem_multiply -1,cntr'length) and sync_i = '1' and drdy_i = '1') then
         
             pgend              <= '1';
             
@@ -587,19 +597,19 @@ begin  -- rtl
          
         if(pgreq_i = '1') then
         
-          mem_addr(c_swc_packet_mem_addr_width-1 downto c_swc_page_offset_width) <= pgaddr_i;
-          mem_addr(c_swc_page_offset_width-1 downto 0)                           <= (others => '0');
+          mem_addr(g_mem_addr_width-1 downto g_page_addr_offset_width) <= pgaddr_i;
+          mem_addr(g_page_addr_offset_width-1 downto 0)                           <= (others => '0');
 --          pgend                                                                  <= '0';
  --         next_page_loaded                                                       <= '1';
           
         elsif(state_write = S_WRITE_DATA) then
           
-          if(mem_addr(c_swc_page_offset_width-1 downto 0) = allones(c_swc_page_offset_width-1 downto 0) ) then
+          if(mem_addr(g_page_addr_offset_width-1 downto 0) = allones(g_page_addr_offset_width-1 downto 0) ) then
 --            pgend            <= '1';
 --            next_page_loaded <= '0';
           else
             
-            mem_addr(c_swc_page_offset_width-1 downto 0) <= std_logic_vector(unsigned(mem_addr(c_swc_page_offset_width-1 downto 0)) + 1);
+            mem_addr(g_page_addr_offset_width-1 downto 0) <= std_logic_vector(unsigned(mem_addr(g_page_addr_offset_width-1 downto 0)) + 1);
                         
           end if;
 
@@ -625,7 +635,7 @@ begin  -- rtl
           end if;
           
           
-          for i in 0 to c_swc_packet_mem_multiply-1 loop
+          for i in 0 to g_packet_mem_multiply-1 loop
             if(i >= to_integer(cntr)) then 
               in_reg(i) <= (others => '0');
             end if;
@@ -637,8 +647,8 @@ begin  -- rtl
           -- entity
 --          if(state_write = S_IDLE) then
 --            cntr <= (others =>'1');
---          elsif(cntr = to_unsigned(c_swc_packet_mem_multiply -1,cntr'length)) then
-          if(cntr = to_unsigned(c_swc_packet_mem_multiply -1,cntr'length)) then
+--          elsif(cntr = to_unsigned(g_packet_mem_multiply -1,cntr'length)) then
+          if(cntr = to_unsigned(g_packet_mem_multiply -1,cntr'length)) then
             cntr     <= (others => '0');
           elsif((state_write = S_READ_LAST_DATA_WORD) and sync_i = '1') then
             cntr      <= (others => '0');
@@ -879,12 +889,12 @@ begin  -- rtl
 --            (not sync_i)) or(pgend and sync_i));-- or (sync_i and (not drdy_i)));-- and not before_sync;
             
          
-  --addr_o <= pgaddr_i & zeros (c_swc_page_offset_width-1 downto 0) when (we_int = '1' and pgreq_i = '1') else mem_addr;
+  --addr_o <= pgaddr_i & zeros (g_page_addr_offset_width-1 downto 0) when (we_int = '1' and pgreq_i = '1') else mem_addr;
   addr_o <= mem_addr;
   pgend_o <= pgend;
   
-  gen_q1 : for i in 0 to c_swc_packet_mem_multiply-1 generate
-    q_o(c_swc_pump_width * (i+1) - 1 downto c_swc_pump_width * i) <= in_reg(i);
+  gen_q1 : for i in 0 to g_packet_mem_multiply-1 generate
+    q_o(g_pump_data_width * (i+1) - 1 downto g_pump_data_width * i) <= in_reg(i);
   end generate gen_q1;
   
   ll_addr_o   <= ll_write_addr;

modules/wrsw_swcore/swc_page_alloc_old.vhd

@@ -109,6 +109,8 @@ entity swc_page_allocator is
     -- number of bits of the page address
     g_page_addr_width: integer := 11; --g_page_addr_bits 
 
+    g_num_ports      : integer ;--:= c_swc_num_ports
+
     -- number of bits of the user count value
     g_usecount_width: integer := 4 --g_use_count_bits 
     );
@@ -397,7 +399,7 @@ begin  -- syn
             -- ========= hystheresis ===========================
             if(nomem = '0' and (free_blocks < 3)) then
               nomem <= '1';
-            elsif(nomem = '1' and (free_blocks > (3*c_swc_num_ports))) then
+            elsif(nomem = '1' and (free_blocks > (3*g_num_ports))) then
               nomem <= '0';
             end if;
             -- ========= =========== ===========================

modules/wrsw_swcore/xswc_core.vhd

@@ -53,7 +53,7 @@ use work.wrsw_shared_types_pkg.all;
 entity xswc_core is
   generic
     ( 
-    g_num_ports             : integer := c_swc_num_ports
+    g_num_ports             : integer := 7 --c_swc_num_ports
     );
   port (
     clk_i   : in std_logic;
@@ -66,14 +66,12 @@ entity xswc_core is
     snk_i : in  t_wrf_sink_in_array(g_num_ports-1 downto 0);
     snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
 
- 
 -------------------------------------------------------------------------------
 -- pWB : output (goes to the Endpoint)
 -------------------------------------------------------------------------------  
 
     src_i : in  t_wrf_source_in_array(g_num_ports-1 downto 0);
     src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
-
     
 -------------------------------------------------------------------------------
 -- I/F with Routing Table Unit (RTU)
@@ -92,7 +90,7 @@ architecture rtl of xswc_core is
     g_mem_size                         : integer ;--:= c_swc_packet_mem_size
     g_page_size                        : integer ;--:= c_swc_page_size
     g_prio_num                         : integer ;--:= c_swc_output_prio_num;
-    g_max_pck_size_width               : integer ;--:= c_swc_max_pck_size_width    
+    g_max_pck_size                     : integer ;--:= c_swc_max_pck_size
     g_num_ports                        : integer ;--:= c_swc_num_ports
     g_data_width                       : integer ;--:= c_swc_data_width
     g_ctrl_width                       : integer ; --:= c_swc_ctrl_width
@@ -117,7 +115,6 @@ architecture rtl of xswc_core is
     snk_i : in  t_wrf_sink_in_array(g_num_ports-1 downto 0);
     snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
 
-
     -------------------------------------------------------------------------------
     -- pWB : output (goes to the Endpoint)
     -------------------------------------------------------------------------------  
@@ -135,30 +132,24 @@ architecture rtl of xswc_core is
     );
    end component;
 
-
-
 begin
 
-
-
-
-
   U_swc_core: swc_core
     generic map( 
-      g_mem_size                         => c_swc_packet_mem_size,
-      g_page_size                        => c_swc_page_size,
-      g_prio_num                         => c_swc_output_prio_num,
-      g_max_pck_size_width               => c_swc_max_pck_size_width,
-      g_num_ports                        => c_swc_num_ports,
-      g_data_width                       => c_swc_data_width,
-      g_ctrl_width                       => c_swc_ctrl_width,
-      g_pck_pg_free_fifo_size            => c_swc_freeing_fifo_size,
-      g_input_block_cannot_accept_data   => "drop_pck", --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
-      g_output_block_per_prio_fifo_size  => c_swc_output_fifo_size,
+      g_mem_size                         => 65536,           -- c_swc_packet_mem_size,
+      g_page_size                        => 64,              -- c_swc_page_size,
+      g_prio_num                         => 8,               -- c_swc_output_prio_num,
+      g_max_pck_size                     => 10 * 1024, --10kB -- c_swc_max_pck_size,
+      g_num_ports                        => 7 ,              -- c_swc_num_ports,
+      g_data_width                       => 16,              -- c_swc_data_width,
+      g_ctrl_width                       => 4,               -- c_swc_ctrl_width,
+      g_pck_pg_free_fifo_size            => (65536/64)/2,    -- c_swc_freeing_fifo_size,
+      g_input_block_cannot_accept_data   => "drop_pck",      --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
+      g_output_block_per_prio_fifo_size  => 64,              -- c_swc_output_fifo_size,
       -- probably useless with new memory      
-      g_packet_mem_multiply              => c_swc_packet_mem_multiply,
-      g_input_block_fifo_size            => c_swc_input_fifo_size,     
-      g_input_block_fifo_full_in_advance => c_swc_fifo_full_in_advance
+      g_packet_mem_multiply              => 16,              -- c_swc_packet_mem_multiply,
+      g_input_block_fifo_size            => 2 *  16,         -- c_swc_input_fifo_size,     
+      g_input_block_fifo_full_in_advance => (2 * 16) - 3     -- c_swc_fifo_full_in_advance
     )
     port map (
       clk_i               => clk_i,

modules/wrsw_swcore/xswc_output_block.vhd

@@ -291,6 +291,9 @@ begin  --  behavoural
     read(i)         <= read_array(i)  when (state = SET_PAGE) else '0';--rx_dreq_i;
       
     PRIO_QUEUE_CTRL : swc_ob_prio_queue
+      generic map(
+        g_per_prio_fifo_size_width => c_per_prio_fifo_size_width -- c_swc_output_fifo_addr_width
+       )
       port map (
         clk_i       => clk_i,
         rst_n_i     => rst_n_i,