use GTX _rdy_ output to reset rx clock domain in the endpoint

Fix for the issue 1063. In short, we need to keep in reset clock alignment fifo
in the endpoint (native Virtex-6 FIFO) until GTX is locked and produces rx
clock. That's what Xilinx document _ug363_ says. Otherwise, if this FIFO is not
reset correctly I get strange behavior like asserting empty_o and almost_full_o
in the same time.

wr-cores @ 77d23a1b

-Subproject commit 56a6681cb8dea06a18db2ed059672761361259bc
+Subproject commit 77d23a1b096ac3320c0ac2ae42fd466cb96d0762

top/bare_top/scb_top_bare.vhd

@@ -660,6 +660,7 @@ begin
           phy_rst_o          => phys_o(i).rst,
           phy_loopen_o       => phys_o(i).loopen,
           phy_enable_o       => phys_o(i).enable,
+          phy_rdy_i          => phys_i(i).rdy,
           phy_ref_clk_i      => phys_i(i).ref_clk,
           phy_tx_data_o      => ep_dbg_data_array(i), -- phys_o(i).tx_data, --
           phy_tx_k_o         => ep_dbg_k_array(i),    -- phys_o(i).tx_k,    -- 

top/bare_top/wrsw_components_pkg.vhd

@@ -62,6 +62,7 @@ package wrsw_components_pkg is
     rx_k         : std_logic_vector(1 downto 0);
     rx_enc_err   : std_logic;
     rx_bitslide  : std_logic_vector(4 downto 0);
+    rdy          : std_logic;
   end record;
 
   type t_phyif_output_array is array(integer range <>) of t_phyif_output;
@@ -136,7 +137,8 @@ package wrsw_components_pkg is
       pad_txn_o      : out std_logic;
       pad_txp_o      : out std_logic;
       pad_rxn_i      : in  std_logic := '0';
-      pad_rxp_i      : in  std_logic := '0');
+      pad_rxp_i      : in  std_logic := '0';
+      rdy_o          : out std_logic);
   end component;
 
   component xwr_pps_gen

top/bare_top/wrsw_top_pkg.vhd

@@ -62,6 +62,7 @@ package wrsw_top_pkg is
     rx_k         : std_logic_vector(1 downto 0);
     rx_enc_err   : std_logic;
     rx_bitslide  : std_logic_vector(4 downto 0);
+    rdy          : std_logic;
   end record;
 
   type t_phyif_output_array is array(integer range <>) of t_phyif_output;
@@ -136,7 +137,8 @@ package wrsw_top_pkg is
       pad_txn_o      : out std_logic;
       pad_txp_o      : out std_logic;
       pad_rxn_i      : in  std_logic := '0';
-      pad_rxp_i      : in  std_logic := '0');
+      pad_rxp_i      : in  std_logic := '0';
+      rdy_o          : out std_logic);
   end component;
 
   component xwr_pps_gen

top/scb_18ports/scb_top_synthesis.vhd

@@ -628,7 +628,8 @@ begin
         pad_txn_o      => gtx_txn_o(i),
         pad_txp_o      => gtx_txp_o(i),
         pad_rxn_i      => gtx_rxn_i(i),
-        pad_rxp_i      => gtx_rxp_i(i));
+        pad_rxp_i      => gtx_rxp_i(i),
+        rdy_o          => from_phys(i).rdy);
 
     from_phys(i).ref_clk <= clk_ref;
   end generate gen_phys_bufr;
@@ -658,7 +659,8 @@ begin
         pad_txn_o      => gtx_txn_o(i),
         pad_txp_o      => gtx_txp_o(i),
         pad_rxn_i      => gtx_rxn_i(i),
-        pad_rxp_i      => gtx_rxp_i(i));
+        pad_rxp_i      => gtx_rxp_i(i),
+        rdy_o          => from_phys(i).rdy);
 
     from_phys(i).ref_clk <= clk_ref;
   end generate gen_phys;

top/scb_8ports/scb_top_synthesis.vhd

@@ -642,7 +642,8 @@ begin
         pad_txn_o      => gtx_txn_o(i),
         pad_txp_o      => gtx_txp_o(i),
         pad_rxn_i      => gtx_rxn_i(i),
-        pad_rxp_i      => gtx_rxp_i(i));
+        pad_rxp_i      => gtx_rxp_i(i),
+        rdy_o          => from_phys(i).rdy);
 
     from_phys(i).ref_clk <= clk_ref;
   end generate gen_phys_bufr;
@@ -672,7 +673,8 @@ begin
         pad_txn_o      => gtx_txn_o(i),
         pad_txp_o      => gtx_txp_o(i),
         pad_rxn_i      => gtx_rxn_i(i),
-        pad_rxp_i      => gtx_rxp_i(i));
+        pad_rxp_i      => gtx_rxp_i(i),
+        rdy_o          => from_phys(i).rdy);
 
     from_phys(i).ref_clk <= clk_ref;
   end generate gen_phys;