From 22e38c232de2746699208e52424451f662c26251 Mon Sep 17 00:00:00 2001
From: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
Date: Mon, 2 Mar 2015 17:53:55 +0100
Subject: [PATCH] use GTX _rdy_ output to reset rx clock domain in the endpoint
Fix for the issue 1063. In short, we need to keep in reset clock alignment fifo
in the endpoint (native Virtex-6 FIFO) until GTX is locked and produces rx
clock. That's what Xilinx document _ug363_ says. Otherwise, if this FIFO is not
reset correctly I get strange behavior like asserting empty_o and almost_full_o
in the same time.
---
ip_cores/wr-cores | 2 +-
top/bare_top/scb_top_bare.vhd | 1 +
top/bare_top/wrsw_components_pkg.vhd | 4 +++-
top/bare_top/wrsw_top_pkg.vhd | 4 +++-
top/scb_18ports/scb_top_synthesis.vhd | 6 ++++--
top/scb_8ports/scb_top_synthesis.vhd | 6 ++++--
6 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/ip_cores/wr-cores b/ip_cores/wr-cores
index 56a6681c..77d23a1b 160000
--- a/ip_cores/wr-cores
+++ b/ip_cores/wr-cores
@@ -1 +1 @@
-Subproject commit 56a6681cb8dea06a18db2ed059672761361259bc
+Subproject commit 77d23a1b096ac3320c0ac2ae42fd466cb96d0762
diff --git a/top/bare_top/scb_top_bare.vhd b/top/bare_top/scb_top_bare.vhd
index a2b07952..5f63af70 100644
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -660,6 +660,7 @@ begin
phy_rst_o => phys_o(i).rst,
phy_loopen_o => phys_o(i).loopen,
phy_enable_o => phys_o(i).enable,
+ phy_rdy_i => phys_i(i).rdy,
phy_ref_clk_i => phys_i(i).ref_clk,
phy_tx_data_o => ep_dbg_data_array(i), -- phys_o(i).tx_data, --
phy_tx_k_o => ep_dbg_k_array(i), -- phys_o(i).tx_k, --
diff --git a/top/bare_top/wrsw_components_pkg.vhd b/top/bare_top/wrsw_components_pkg.vhd
index 6d958a47..59f0b470 100644
--- a/top/bare_top/wrsw_components_pkg.vhd
+++ b/top/bare_top/wrsw_components_pkg.vhd
@@ -62,6 +62,7 @@ package wrsw_components_pkg is
rx_k : std_logic_vector(1 downto 0);
rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(4 downto 0);
+ rdy : std_logic;
end record;
type t_phyif_output_array is array(integer range <>) of t_phyif_output;
@@ -136,7 +137,8 @@ package wrsw_components_pkg is
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
- pad_rxp_i : in std_logic := '0');
+ pad_rxp_i : in std_logic := '0';
+ rdy_o : out std_logic);
end component;
component xwr_pps_gen
diff --git a/top/bare_top/wrsw_top_pkg.vhd b/top/bare_top/wrsw_top_pkg.vhd
index 3a1b127a..4c824eeb 100644
--- a/top/bare_top/wrsw_top_pkg.vhd
+++ b/top/bare_top/wrsw_top_pkg.vhd
@@ -62,6 +62,7 @@ package wrsw_top_pkg is
rx_k : std_logic_vector(1 downto 0);
rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(4 downto 0);
+ rdy : std_logic;
end record;
type t_phyif_output_array is array(integer range <>) of t_phyif_output;
@@ -136,7 +137,8 @@ package wrsw_top_pkg is
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
- pad_rxp_i : in std_logic := '0');
+ pad_rxp_i : in std_logic := '0';
+ rdy_o : out std_logic);
end component;
component xwr_pps_gen
diff --git a/top/scb_18ports/scb_top_synthesis.vhd b/top/scb_18ports/scb_top_synthesis.vhd
index 80cc9226..7f262fd9 100644
--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
@@ -628,7 +628,8 @@ begin
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
- pad_rxp_i => gtx_rxp_i(i));
+ pad_rxp_i => gtx_rxp_i(i),
+ rdy_o => from_phys(i).rdy);
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys_bufr;
@@ -658,7 +659,8 @@ begin
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
- pad_rxp_i => gtx_rxp_i(i));
+ pad_rxp_i => gtx_rxp_i(i),
+ rdy_o => from_phys(i).rdy);
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys;
diff --git a/top/scb_8ports/scb_top_synthesis.vhd b/top/scb_8ports/scb_top_synthesis.vhd
index c69e2b68..d68f8db6 100644
--- a/top/scb_8ports/scb_top_synthesis.vhd
+++ b/top/scb_8ports/scb_top_synthesis.vhd
@@ -642,7 +642,8 @@ begin
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
- pad_rxp_i => gtx_rxp_i(i));
+ pad_rxp_i => gtx_rxp_i(i),
+ rdy_o => from_phys(i).rdy);
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys_bufr;
@@ -672,7 +673,8 @@ begin
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
- pad_rxp_i => gtx_rxp_i(i));
+ pad_rxp_i => gtx_rxp_i(i),
+ rdy_o => from_phys(i).rdy);
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys;
--
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