swcore[v2->v3 port]: working with ip_cores/general-cores altera

modules/wrsw_swcore/swc_multiport_linked_list.vhd

@@ -149,7 +149,7 @@ architecture syn of swc_multiport_linked_list is
   signal free_pck_read_done           : std_logic_vector(c_swc_num_ports-1 downto 0);
 
   signal ram_zeros                 : std_logic_vector( c_swc_page_addr_width - 1 downto 0);
-  signal ram_ones                  : std_logic_vector((c_swc_page_addr_width)/8 - 1 downto 0);
+  signal ram_ones                  : std_logic_vector((c_swc_page_addr_width+7)/8 - 1 downto 0);
   
 begin  -- syn
 

modules/wrsw_swcore/swc_page_alloc.vhd

@@ -308,12 +308,12 @@ begin  -- syn
       aa_i   => usecnt_mem_wraddr,
       qa_o   => open,
       wea_i  => usecnt_mem_wr,
-      bwea_i => ones((g_use_count_bits)/8 -1 downto 0),--ones((g_use_count_bits+7)/8 -1 downto 0),
+      bwea_i => ones((g_use_count_bits+7)/8 -1 downto 0),--ones((g_use_count_bits+7)/8 -1 downto 0),
 
       ab_i   => usecnt_mem_rdaddr,
       qb_o   => usecnt_mem_rddata,
       db_i   => ones(g_use_count_bits-1 downto 0),
-      bweb_i => ones((g_use_count_bits)/8-1 downto 0), --ones((g_use_count_bits+7)/8-1 downto 0),
+      bweb_i => ones((g_use_count_bits+7)/8-1 downto 0), --ones((g_use_count_bits+7)/8-1 downto 0),
       web_i  => '0'
       );
 

testbench/swcore/.gitignore

-*.wlf
+vsim.wlf

testbench/swcore/Manifest.py

@@ -9,9 +9,9 @@ vlog_opt="+incdir+../../../sim "
 
 modules = {"local":
 		[ 
-		  "../../platform/altera",
-		  "../../platform/genrams/altera",
-		  #"../../ip_cores/general-cores/modules/genrams/",
+		  #"../../platform/altera",
+		  #"../../platform/genrams/altera",
+		  "../../ip_cores/general-cores/modules/genrams/",
 		  "../../modules/wrsw_swcore",
 		],
 	    #"git" :