[TOP_SIM] added *more fancy* simulation of links failure

testbench/scb_top/main.sv

@@ -64,6 +64,7 @@ module main;
    CSimDrv_HWDU hwdu;
    
    reg [g_num_ports-1:0] ep_ctrl;
+   reg [15:0]            ep_failure_type = 'h00;
    
    // prameters to create some gaps between pks (not work really well)
    // default settings
@@ -208,6 +209,7 @@ module main;
    int lacp_df_hp_id                        = 0;
    int lacp_df_br_id                        = 2;
    int lacp_df_un_id                        = 1;
+   
    /** ***************************   test scenario 1  ************************************* **/ 
   /*
    * testing switch over between ports 0,1,2
@@ -1423,6 +1425,7 @@ module main;
   end
 */
    /** ***************************   test scenario 49  ************************************* **/ 
+   /** ***************************      (FIXED BUG)    ************************************* **/ 
   /*
    * testing switch over between ports 1,2 on the "upper switch" -> the one which is sending
    * onto two ports 
@@ -1430,7 +1433,7 @@ module main;
    * to the rendundant link aggregation
    * 
    **/
-//*
+/*
   initial begin
     portUnderTest        = 18'b0000000000010000000;
     portRtuEnabled       = 18'b0000000000010000110;
@@ -1446,6 +1449,30 @@ module main;
     g_enable_pck_gaps    = 0;
     g_force_payload_size = 512;
   end
+*/
+   /** ***************************   test scenario 50  ************************************* **/ 
+  /*
+   * testing switch over between ports 1,2 
+   * simulating ungraceful loss of physic signal....
+   * 
+   **/
+//*
+  initial begin
+    portUnderTest        = 18'b000000000000000110;
+    g_tru_enable         = 1;
+    g_failure_scenario   = 11;
+                         // tx  ,rx ,opt
+    trans_paths[1]       = '{1  ,6 , 4 };
+    trans_paths[2]       = '{2  ,7 , 4 };
+    repeat_number        = 30;
+    g_active_port        = 1;
+    g_backup_port        = 2;    
+    ep_failure_type      = 'h01;
+    tries_number         = 1;
+    tru_config_opt       = 3;
+    g_enable_pck_gaps    = 0;
+    g_force_payload_size = 512;
+  end
 //*/
 //////////////////////////////////////////////////////////////////////////////////////////////
 //////////////////////////////////////////////////////////////////////////////////////////////
@@ -1817,7 +1844,8 @@ module main;
               .rst_n_i(rst_n),
               .cpu_irq(cpu_irq),
               .clk_swc_mpm_core_i(clk_swc_mpm_core),
-              .ep_ctrl_i(ep_ctrl)
+              .ep_ctrl_i(ep_ctrl),
+              .ep_failure_type(ep_failure_type)
               );
 
    
@@ -2113,6 +2141,7 @@ module main;
       begin 
         ep_ctrl[gg] = 'b1; 
       end
+      
       repeat(200) @(posedge clk_sys);
 
       $display("Startup!");

testbench/scb_top/scb_top_sim_svwrap.svh

@@ -46,16 +46,19 @@ module scb_top_sim_svwrap
    rst_n_i,
    cpu_irq,
    clk_swc_mpm_core_i,
-   ep_ctrl_i
+   ep_ctrl_i,
+   ep_failure_type
    );
 
    parameter g_num_ports = 6;
    
-
+   reg [15:0] tx_data_invalid[g_num_ports];
+   reg [ 1:0] tx_k_invalid[g_num_ports];
    
    input clk_sys_i, clk_ref_i,rst_n_i,clk_swc_mpm_core_i;
    input bit[g_num_ports-1:0] ep_ctrl_i;
    output cpu_irq;
+   input [15:0] ep_failure_type;
 
    wire [g_num_ports-1:0] rbclk;
    
@@ -244,19 +247,20 @@ module scb_top_sim_svwrap
            end // for (i=0; i<g_num_ports; i++)
       endgenerate
 
-
    generate
       genvar j;
-
-
-      
+       
+     
       for(j=0;j<g_num_ports;j++) begin
          assign rbclk[j] = clk_ref_phys[j];
          
          ///////////////// nasty hack by Maciej /////////////////
          // causing sync error in the Switch 
-         assign td[18 * j + 15 : 18 * j]      = ep_ctrl_i[j] ? phys_out[j].tx_data :  'h00BC;
-         assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k    : 2'b01;
+//          assign td[18 * j + 15 : 18 * j]      = ep_ctrl_i[j] ? phys_out[j].tx_data :  'h00BC;
+//          assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k    : 2'b01;
+         assign td[18 * j + 15 : 18 * j]      = ep_ctrl_i[j] ? phys_out[j].tx_data : tx_data_invalid[j];
+         assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k    : tx_k_invalid[j];
+         
          // causing transmission error in the driving simulation
          assign phys_in[j].tx_enc_err         = ~ep_ctrl_i[j];
          ///////////////////////////////////////////////////////
@@ -280,7 +284,34 @@ module scb_top_sim_svwrap
                                           phys_out[j].tx_data);
          end
          
-      end
+
+         always@(posedge clk_sys_i) begin
+            integer jj;
+            if(ep_ctrl_i[j] == 1) begin 
+              tx_data_invalid[j] = 'h00BC;
+              tx_k_invalid[j]    = 2'b01 ;  
+              jj = 0;               
+            end
+            else begin
+              if(ep_failure_type == 1) begin
+                $display("Link failure type: 1 [generate some random noise, starting with data='h00BC, k = 'b01]");
+                while(jj++<100) begin
+                  tx_data_invalid[j] = 'h00BC + jj;
+                  tx_k_invalid[j]    = 2'b01 & jj;
+                  @(posedge clk_sys_i);
+                end
+                tx_data_invalid[j] = 'h00BC;
+                tx_k_invalid[j]    = 2'b01 ;              
+              end
+              else begin //including 0
+                $display("Link failure type: 0 [simply off the link: data='h00BC, k = 'b01]");
+                tx_data_invalid[j] = 'h00BC;
+                tx_k_invalid[j]    = 2'b01 ;
+              end
+            end;
+         end 
+
+      end 
    endgenerate