[GEN_COREs] cherry-picked commit by Greg to make the sythesis work on ISE 14.5

general-cores @ 40c3c491

-Subproject commit 18fa7851a47d149d5562a92e0fa36b05286628e0
+Subproject commit 40c3c491f0183be30e7946a3cb33bf54527d036f

top/bare_top/scb_top_bare.vhd

@@ -139,7 +139,7 @@ end scb_top_bare;
 
 architecture rtl of scb_top_bare is
 
-  constant c_GW_VERSION    : std_logic_vector(31 downto 0) := x"10_05_13_01"; --DD_MM_YY_VV
+  constant c_GW_VERSION    : std_logic_vector(31 downto 0) := x"10_05_13_02"; --DD_MM_YY_VV
   constant c_NUM_WB_SLAVES : integer := 16;
   constant c_NUM_PORTS     : integer := g_num_ports;
   constant c_MAX_PORTS     : integer := 18;