White Rabbit low jitter

Project exploring different ways of creating the best possible jitter performance and lowest Allan Deviation.

The aim of this project is:

• Characterize the perfomance of the current White Rabbit time distribution system
• Find the limitations of the current implementation
• Propose a new implementation for both the WR Switch and WR End Node

Detailed informations

• Phase-noise-and-ADEV-of-the-WR-Switch-using-different-TCVCXOs

Documents

• M. Rizzi et al., White rabbit clock characteristics 2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS), Stockholm, 2016, pp. 1-6. doi: 10.1109/ISPCS.2016.7579514
• M. Rizzi, et al. White Rabbit Clock Synchronization: Ultimate Limits on Close-In Phase Noise and Short-Term Stability Due to FPGA Implementation in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 65, no. 9, pp. 1726-1737, Sept. 2018. doi: 10.1109/TUFFC.2018.2851842
• White Rabbit Switch performance in Grandmaster mode (please refer the IEEE "White rabbit clock characteristics" paper for citations)
• DAC additive phase noise
• DDMTD Report
• Gigabit transceiver phase noise and stability report_

Boards

• WRS Low Jitter Daughterboard - project
• Daughterboard-for-the-White-Rabbit-Switch
  • outdated

Contacts

• Mattia Rizzi

Status

06 March 2017