The current release of the White Rabbit Switch (WRS) in Grandmaster (GM)
mode has suboptimal performance on both jitter (9ps RMS 1-100kHz) and
Allan Deviation (1.4E-11 τ=1s), as presented in the last WR Workshop.
The following report will briefly introduce the WRS clocking scheme, the
origin of the current performance in GM mode and the improvements with
some hardware modifications (done on a WRS PCB V3.4 board).
The first hardware modification allows the direct distribution of the
external reference clock as Layer 1 (L1) clock without using the
“SoftPLL “ (i.e. a digital implementation of the PLL used to align the
WR clock - local PTP clock - to the external reference clock when
operating in GM mode, or to the L1 Rx clock when operating in Boundary
mode). This hardware modification achieved a measured Allan Deviation
(ADEV) of 4-5E-13 τ=1s and an RMS jitter of 5.6ps.
The second hardware modification (orthogonal to the first one) keeps the
SoftPLL fully working, using an external board to perform a clock
synthesis currently done inside the FPGA, reaching an ADEV of 2E-12 τ=1s
and an RMS jitter of 2.3ps. Since the clock alignment mechanism is
independent from the mode in use (GM or Boundary), any performance
limitation found in GM mode will be there also in Boundary mode.
This document explain the additive phase noise due to quantization noise
in a theoretically way. Moreover, it provides phase noise values using
the default mounted DAC (AD5662, 16 bits), taking into account also the
voltage noise due to the DAC output stage. The result of the calculation
is that AD5662 is still fine for cheap, AT-cut, voltage controlled
crystal oscillators (VCXOs). In order to optimally control an OCXO with
SC-cut crystal, a DAC resolution of 20+ bits is recommended.
The scope of the following document is to evaluate the phase noise and
stability floor of the Digital Dual Mixer Time Difference (DDMTD) phase
detector in the WR PLL architecture. The measurement has been done on
the WR Switch (Virtex-6) The effect of the DDMTD common clock noise on
the phase noise floor is modelled mathematically and verified
The experimental results show a phase noise floor of -108 dBc/Hz (10MHz
carrier) combined with a flicker noise (1/f noise) of -100dBc/Hz at 1Hz
(flicker corner frequency at 5Hz). The flicker noise has been traced to
the LVDS input clock buffer of the FPGA.
The DDMTD is able to provide 4 ps single-shot precision (1 σ) with a
measurement rate up to 3.8 kHz
The stability of the DDMTD has been characterized with Modified Allan
Deviation (MDEV) and Allan Deviation (ADEV). The results are:
MDEV 4E-13 at Tau=1s for Equivalent Noise BW of 50Hz,
ADEV, is depending on the Equivalent Noise Bandwidth,
4E-13 at Tau=1s for Equivalent Noise BW of 0.5Hz and
The scope of this document is to investigate the phase noise and
stability of the WR Switch transceivers. Along with the Digital DMTD
phase detector, they constitute the core of the WR time dissemination
performance. Moreover, the report includes an analysis of the stability
of the Axcen SFPs (commonly used in WR installations).
The stability analysis of the Axcen SFPs resulted in a Modified Allan
Deviation of less than 1E-13 with Tau=1s..10s. The stability is better
than H-Maser clock.
The GTX transceivers have a Modified Allan Deviation of 4E-13/s,
dominated by flicker noise from Tau=0.1s to 100s. The stability of the
GTX transceiver is equal to the stability of the phase detector used by
the WR PLL (DDMTD). Hence, the overall stability of the WR Switch
configured as a boundary clock is equally dominated by the GTX and by